1 /* 2 * Arm SCP/MCP Software 3 * Copyright (c) 2019-2021, Arm Limited and Contributors. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 * 7 * Description: 8 * PL35x NAND Flash Memory Controller register definitions 9 */ 10 11 #ifndef PL35X_H 12 #define PL35X_H 13 14 #include "juno_mmap.h" 15 16 #include <fwk_macros.h> 17 18 #include <stdint.h> 19 20 /* 21 * PL35X register definitions 22 */ 23 struct pl35x_reg { 24 FWK_R uint32_t MEMC_STATUS; 25 FWK_R uint32_t MEMIF_CONFIG; 26 FWK_W uint32_t MEM_CFG_SET; 27 FWK_W uint32_t MEM_CFG_CLR; 28 FWK_W uint32_t DIRECT_CMD; 29 FWK_W uint32_t SET_CYCLES; 30 FWK_W uint32_t SET_OPMODE; 31 uint8_t RESERVED1[0x20 - 0x1C]; 32 FWK_RW uint32_t REFRESH0; 33 FWK_RW uint32_t REFRESH1; 34 uint8_t RESERVED2[0x100 - 0x28]; 35 36 struct { /* CS registers */ 37 FWK_R uint32_t CYCLES; 38 FWK_R uint32_t OPMODE; 39 uint32_t RESERVED[6]; 40 } CS[8]; 41 42 FWK_R uint32_t USER_STATUS; 43 FWK_W uint32_t USER_CONFIG; 44 uint8_t RESERVED3[0x300 - 0x208]; 45 46 struct pl35x_ecc_reg { /* ECC registers */ 47 FWK_RW uint32_t STATUS; 48 FWK_RW uint32_t CONFIG; 49 FWK_RW uint32_t MEMCMD0; 50 FWK_RW uint32_t MEMCMD1; 51 FWK_W uint32_t ADDR0; 52 FWK_W uint32_t ADDR1; 53 FWK_RW uint32_t BLOCK0; 54 FWK_RW uint32_t BLOCK1; 55 FWK_RW uint32_t BLOCK2; 56 FWK_RW uint32_t BLOCK3; 57 FWK_RW uint32_t EXTRA_BLOCK; 58 uint32_t RESERVED[53]; 59 } ECC[2]; 60 61 uint8_t RESERVED4[0xE00 - 0x500]; 62 FWK_RW uint32_t INT_CFG; 63 FWK_RW uint32_t INT_INPUTS; 64 FWK_RW uint32_t INT_OUTPUTS; 65 uint8_t RESERVED5[0xFE0 - 0xE0C]; 66 FWK_R uint32_t PERIPH_ID_0; 67 FWK_R uint32_t PERIPH_ID_1; 68 FWK_R uint32_t PERIPH_ID_2; 69 FWK_R uint32_t PERIPH_ID_3; 70 FWK_R uint32_t PCELL_ID_0; 71 FWK_R uint32_t PCELL_ID_1; 72 FWK_R uint32_t PCELL_ID_2; 73 FWK_R uint32_t PCELL_ID_3; 74 }; 75 76 #define SMC ((struct pl35x_reg *) SMC_BASE) 77 78 #endif /* PL35X_H */ 79