1 /* 2 * Arm SCP/MCP Software 3 * Copyright (c) 2019-2021, Arm Limited and Contributors. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 * 7 * Description: 8 * Juno DMC-400 module. 9 */ 10 11 #ifndef MOD_JUNO_DMC400_H 12 #define MOD_JUNO_DMC400_H 13 14 #include "scp_config.h" 15 16 #include <mod_timer.h> 17 18 #include <fwk_id.h> 19 #include <fwk_macros.h> 20 21 #include <stdbool.h> 22 #include <stdint.h> 23 24 /*! 25 * \ingroup GroupJunoModule 26 * \defgroup GroupJunoDMC400 DMC-400 Driver 27 * \{ 28 */ 29 30 /*! 31 * \brief Time-out when programming the DDR in us. 32 */ 33 #define TIMEOUT_DMC400_US (1000 * 1000) 34 35 /*! 36 * \brief Delay after remove DDR PORESET in cycles. 37 */ 38 #define DELAY_DDR_PORESET_CYCLES 10 39 40 /*! 41 * \brief Delay after direct commands to initialize LPDDR3 in cycles. 42 */ 43 #define DELAY_DDR_INIT_LPDDR3_CYCLES 100 44 45 /*! 46 * \brief User config twrdata_delay. 47 */ 48 #define DMC_USER_CONFIG_TWRDATA_DELAY UINT32_C(0x00000001) 49 50 /*! 51 * \brief User config twrdata_en_delay. 52 */ 53 #define DMC_USER_CONFIG_TWRDATA_EN_DELAY UINT32_C(0x00000002) 54 55 /*! 56 * \brief DMC-400 register definitions. 57 */ 58 struct mod_juno_dmc400_reg { 59 /*! 60 * \cond 61 */ 62 FWK_R uint32_t MEMC_STATUS; 63 FWK_R uint32_t MEMC_CONFIG; 64 FWK_W uint32_t MEMC_CMD; 65 uint8_t RESERVED0[0x010 - 0x00C]; 66 FWK_RW uint32_t ADDRESS_CONTROL; 67 FWK_RW uint32_t DECODE_CONTROL; 68 FWK_RW uint32_t FORMAT_CONTROL; 69 uint8_t RESERVED1[0x020 - 0x01C]; 70 FWK_RW uint32_t LOW_POWER_CONTROL; 71 uint8_t RESERVED2[0x030 - 0x024]; 72 FWK_RW uint32_t TURNAROUND_PRIORITY; 73 FWK_RW uint32_t HIT_PRIORITY; 74 FWK_RW uint32_t QOS0_CONTROL; 75 FWK_RW uint32_t QOS1_CONTROL; 76 FWK_RW uint32_t QOS2_CONTROL; 77 FWK_RW uint32_t QOS3_CONTROL; 78 FWK_RW uint32_t QOS4_CONTROL; 79 FWK_RW uint32_t QOS5_CONTROL; 80 FWK_RW uint32_t QOS6_CONTROL; 81 FWK_RW uint32_t QOS7_CONTROL; 82 FWK_RW uint32_t QOS8_CONTROL; 83 FWK_RW uint32_t QOS9_CONTROL; 84 FWK_RW uint32_t QOS10_CONTROL; 85 FWK_RW uint32_t QOS11_CONTROL; 86 FWK_RW uint32_t QOS12_CONTROL; 87 uint8_t RESERVED3[0x070 - 0x06C]; 88 FWK_RW uint32_t QOS13_CONTROL; 89 FWK_RW uint32_t QOS14_CONTROL; 90 FWK_RW uint32_t QOS15_CONTROL; 91 FWK_RW uint32_t TIMEOUT_CONTROL; 92 FWK_RW uint32_t QUEUE_CONTROL; 93 uint8_t RESERVED4[0x088 - 0x084]; 94 FWK_RW uint32_t WRITE_PRIORITY_CONTROL; 95 FWK_RW uint32_t WRITE_PRIORITY_CONTROL2; 96 FWK_RW uint32_t READ_PRIORITY_CONTROL; 97 FWK_RW uint32_t READ_PRIORITY_CONTROL2; 98 FWK_RW uint32_t ACCESS_ADDRESS_MATCH_31_00; 99 FWK_RW uint32_t ACCESS_ADDRESS_MATCH_63_32; 100 FWK_RW uint32_t ACCESS_ADDRESS_MASK_31_00; 101 FWK_RW uint32_t ACCESS_ADDRESS_MASK_63_32; 102 uint8_t RESERVED5[0x100 - 0x0A8]; 103 FWK_R uint32_t CHANNEL_STATUS; 104 uint8_t RESERVED6[0x108 - 0x104]; 105 FWK_W uint32_t DIRECT_CMD; 106 uint8_t RESERVED7[0x110 - 0x10C]; 107 FWK_R uint32_t MR_DATA; 108 uint8_t RESERVED8[0x120 - 0x114]; 109 FWK_RW uint32_t REFRESH_CONTROL; 110 uint8_t RESERVED9[0x128 - 0x124]; 111 FWK_RW uint32_t INTERRUPT_CONTROL; 112 uint8_t RESERVED10[0x130 - 0x12C]; 113 FWK_W uint32_t INTERRUPT_CLR; 114 uint8_t RESERVED11[0x138 - 0x134]; 115 FWK_R uint32_t INTERRUPT_STATUS; 116 uint8_t RESERVED12[0x140 - 0x13C]; 117 FWK_R uint32_t INTERRUPT_INFO; 118 uint8_t RESERVED13[0x148 - 0x144]; 119 FWK_RW uint32_t MODE_CONTROL; 120 uint8_t RESERVED14[0x200 - 0x14C]; 121 FWK_RW uint32_t T_REFI; 122 FWK_RW uint32_t T_RFC; 123 FWK_RW uint32_t T_MRR; 124 FWK_RW uint32_t T_MRW; 125 uint8_t RESERVED15[0x218 - 0x210]; 126 FWK_RW uint32_t T_RCD; 127 FWK_RW uint32_t T_RAS; 128 FWK_RW uint32_t T_RP; 129 FWK_RW uint32_t T_RPALL; 130 FWK_RW uint32_t T_RRD; 131 FWK_RW uint32_t T_FAW; 132 FWK_RW uint32_t READ_LATENCY; 133 FWK_RW uint32_t T_RTR; 134 FWK_RW uint32_t T_RTW; 135 FWK_RW uint32_t T_RTP; 136 FWK_RW uint32_t WRITE_LATENCY; 137 FWK_RW uint32_t T_WR; 138 FWK_RW uint32_t T_WTR; 139 FWK_RW uint32_t T_WTW; 140 FWK_RW uint32_t T_ECKD; 141 FWK_RW uint32_t T_XCKD; 142 FWK_RW uint32_t T_EP; 143 FWK_RW uint32_t T_XP; 144 FWK_RW uint32_t T_ESR; 145 FWK_RW uint32_t T_XSR; 146 FWK_RW uint32_t T_SRCKD; 147 FWK_RW uint32_t T_CKSRD; 148 uint8_t RESERVED16[0x300 - 0x270]; 149 FWK_RW uint32_t T_RDDATA_EN; 150 FWK_RW uint32_t T_PHYWRLAT; 151 FWK_RW uint32_t RDLVL_CONTROL; 152 FWK_RW uint32_t RDLVL_MRS; 153 FWK_W uint32_t RDLVL_DIRECT; 154 uint8_t RESERVED17[0x318 - 0x314]; 155 FWK_RW uint32_t T_RDLVL_EN; 156 FWK_RW uint32_t T_RDLVL_RR; 157 uint8_t RESERVED18[0x328 - 0x320]; 158 FWK_RW uint32_t WRLVL_CONTROL; 159 FWK_RW uint32_t WRLVL_MRS; 160 FWK_W uint32_t WRLVL_DIRECT; 161 uint8_t RESERVED19[0x338 - 0x334]; 162 FWK_RW uint32_t T_WRLVL_EN; 163 FWK_RW uint32_t T_WRLVL_WW; 164 uint8_t RESERVED20[0x348 - 0x340]; 165 FWK_RW uint32_t PHY_CONTROL_POWER; 166 uint8_t RESERVED21[0x350 - 0x34C]; 167 FWK_RW uint32_t PHY_UPDATE_CONTROL; 168 uint8_t RESERVED22[0x358 - 0x354]; 169 FWK_RW uint32_t T_LPRESP; 170 uint8_t RESERVED23[0x400 - 0x35C]; 171 FWK_R uint32_t USER_STATUS; 172 FWK_RW uint32_t USER_CONFIG0; 173 FWK_RW uint32_t USER_CONFIG1; 174 uint8_t RESERVED24[0xE00 - 0x40C]; 175 FWK_RW uint32_t INTEG_CFG; 176 uint8_t RESERVED25[0xE08 - 0xE04]; 177 FWK_W uint32_t INTEG_OUTPUTS; 178 uint8_t RESERVED26[0xFD0 - 0xE0C]; 179 FWK_R uint32_t PERIPH_ID_4; 180 uint8_t RESERVED27[0xFE0 - 0xFD4]; 181 FWK_R uint32_t PERIPH_ID_0; 182 FWK_R uint32_t PERIPH_ID_1; 183 FWK_R uint32_t PERIPH_ID_2; 184 FWK_R uint32_t PERIPH_ID_3; 185 FWK_R uint32_t COMPONENT_ID_0; 186 FWK_R uint32_t COMPONENT_ID_1; 187 FWK_R uint32_t COMPONENT_ID_2; 188 FWK_R uint32_t COMPONENT_ID_3; 189 /*! 190 * \endcond 191 */ 192 }; 193 194 /*! 195 * \brief Mask used to issue a GO command (CONFIG to READY state). 196 */ 197 #define DMC400_CMD_GO UINT32_C(0x00000003) 198 199 /*! 200 * \brief Mask used to issue a CONFIGURE command. 201 */ 202 #define DMC400_CMD_CONFIG UINT32_C(0x00000000) 203 204 /*! 205 * \brief Mask used to issue a SLEEP command. 206 */ 207 #define DMC400_CMD_SLEEP UINT32_C(0x00000001) 208 209 /*! 210 * \brief Mask used for the memory controller status bitfield. 211 */ 212 #define DMC_MEMC_STATUS UINT32_C(0x00000003) 213 214 /*! 215 * \brief Create the ADDRESS_CONTROL value. 216 * 217 * \param CHANN Number of channel address bits. 218 * \param CHIP Number of chip-select bits on each interface. 219 * \param BANK Number of bank address bits. 220 * \param ROW Number of row address bits. 221 * \param COL Number of column address bits. 222 * 223 * \return The ADDRESS_CONTROL value. 224 */ 225 #define ADDRESS_CONTROL_VAL(CHANN, CHIP, BANK, ROW, COL) (((CHANN) << 28) | \ 226 ((CHIP) << 24) | \ 227 ((BANK) << 16) | \ 228 ((ROW) << 8) | \ 229 (COL)) 230 231 /*! 232 * \brief Mask used for CRNTCLKDIV bitfield. 233 */ 234 #define DMCCLK_CONTROL_CRNTCLKDIV UINT32_C(0x000F0000) 235 236 /*! 237 * \brief Mask used for CRNTCLK bitfield. 238 */ 239 #define DMCCLK_CONTROL_CRNTCLK UINT32_C(0x0000F000) 240 241 /*! 242 * \brief Mask used for CLKDIV bitfield. 243 */ 244 #define DMCCLK_CONTROL_CLKDIV UINT32_C(0x000000F0) 245 246 /*! 247 * \brief Mask used for CLKSEL bitfield. 248 */ 249 #define DMCCLK_CONTROL_CLKSEL UINT32_C(0x0000000F) 250 251 /*! 252 * \brief Setting used to request SYSINCLK as a clock source. 253 */ 254 #define DMCCLK_CONTROL_CLKSEL_SYSINCLK UINT32_C(0x00000002) 255 256 /*! 257 * \brief User config core_prstn. 258 */ 259 #define DMC_USER_CONFIG_CORE_PRSTN UINT32_C(0x00000010) 260 261 /*! 262 * \brief User config core_srstn. 263 */ 264 #define DMC_USER_CONFIG_CORE_SRSTN UINT32_C(0x00000020) 265 266 /*! 267 * \brief User config dfi_init_start. 268 */ 269 #define DMC_USER_CONFIG_DFI_INIT_START UINT32_C(0x00000040) 270 271 /*! 272 * \brief User status dfi_init_complete_0. 273 */ 274 #define DMC_USER_STATUS_DFI_INIT_COMPLETE_0 UINT32_C(0x00000004) 275 276 /*! 277 * \brief User status dfi_init_complete_1. 278 */ 279 #define DMC_USER_STATUS_DFI_INIT_COMPLETE_1 UINT32_C(0x00000040) 280 281 /*! 282 * \brief State information for memory channel 0 mask. 283 */ 284 #define DMC_CHANNEL_STATUS_M0_MASK UINT32_C(0x0000000F) 285 286 /*! 287 * \brief State information for memory channel 1 mask. 288 */ 289 #define DMC_CHANNEL_STATUS_M1_MASK UINT32_C(0x000000F0) 290 291 /*! 292 * \brief Memory channel 0 IDLE state bit. 293 */ 294 #define DMC_CHANNEL_STATUS_M0_IDLE UINT32_C(0x00000002) 295 296 /*! 297 * \brief Memory channel 1 IDLE state bit. 298 */ 299 #define DMC_CHANNEL_STATUS_M1_IDLE UINT32_C(0x00000020) 300 301 /*! 302 * \brief Mask used to issue an AUTOREFRESH command. 303 */ 304 #define DIRECT_CMD_AUTOREFRESH UINT32_C(0x30000000) 305 306 /*! 307 * \brief Target memory channel 0. 308 */ 309 #define DIRECT_CMD_CHANNEL_0_ADDR UINT32_C(0U << 24) 310 311 /*! 312 * \brief Target memory channel 1. 313 */ 314 #define DIRECT_CMD_CHANNEL_1_ADDR UINT32_C(1U << 24) 315 316 /*! 317 * \brief Target chip select 0. 318 */ 319 #define DIRECT_CMD_CHIP_0_ADDR UINT32_C(0U << 20) 320 321 /*! 322 * \brief Target chip select 1. 323 */ 324 #define DIRECT_CMD_CHIP_1_ADDR UINT32_C(1U << 20) 325 326 /*! 327 * \brief Program to send a request for write leveling training. 328 */ 329 #define WRITE_LEVELING_REQUEST_SEND UINT32_C(0x00000001) 330 331 /*! 332 * \brief Program target channel 0 for write leveling training. 333 */ 334 #define WRITE_LEVELING_CHANNEL_0 UINT32_C(0U << 28) 335 336 /*! 337 * \brief Program target channel 1 for write leveling training. 338 */ 339 #define WRITE_LEVELING_CHANNEL_1 UINT32_C(1U << 28) 340 341 /*! 342 * \brief Program target chip 0 for write leveling training. 343 */ 344 #define WRITE_LEVELING_CHIP_0 UINT32_C(0U << 24) 345 346 /*! 347 * \brief Program target chip 1 for write leveling training. 348 */ 349 #define WRITE_LEVELING_CHIP_1 UINT32_C(1U << 24) 350 351 /*! 352 * \brief Send a request for read gate training. 353 */ 354 #define READ_GATE_TRAINING_REQUEST_SEND UINT32_C(0x00000002) 355 356 /*! 357 * \brief Send a request for read eye training. 358 */ 359 #define READ_EYE_TRAINING_REQUEST_SEND UINT32_C(0x00000001) 360 361 /*! 362 * \brief Program target channel 0 for read leveling training. 363 */ 364 #define READ_LEVELING_CHANNEL_0 UINT32_C(0U << 28) 365 366 /*! 367 * \brief Program target channel 1 for read leveling training. 368 */ 369 #define READ_LEVELING_CHANNEL_1 UINT32_C(1U << 28) 370 371 /*! 372 * \brief Program target chip 0 for read leveling training. 373 */ 374 #define READ_LEVELING_CHIP_0 UINT32_C(0U << 24) 375 376 /*! 377 * \brief Program target chip 1 for read leveling training. 378 */ 379 #define READ_LEVELING_CHIP_1 UINT32_C(1U << 24) 380 381 /*! 382 * \brief DMC-400 module configuration. 383 */ 384 struct mod_juno_dmc400_module_config { 385 /*! 386 * \brief Element identifier of the timer used for time-out when programming 387 * the DMC-400. 388 */ 389 fwk_id_t timer_id; 390 391 /*! DDR PHY module identifier */ 392 fwk_id_t ddr_phy_module_id; 393 394 /*! DDR PHY API identifier */ 395 fwk_id_t ddr_phy_api_id; 396 }; 397 398 /*! 399 * \brief Element configuration. 400 */ 401 struct mod_juno_dmc400_element_config { 402 /*! Base address of the DMC-400 device's registers */ 403 uintptr_t dmc; 404 405 /*! Element identifier of the first DDR PHY-400 device */ 406 fwk_id_t ddr_phy_0_id; 407 408 /*! Element identifier of the second DDR PHY-400 device */ 409 fwk_id_t ddr_phy_1_id; 410 411 /*! Version-specific address control */ 412 uint32_t address_control; 413 414 /*! Version-specific chip count */ 415 uint32_t ddr_chip_count; 416 417 /*! Flag indicating whether the current platform is an FVP */ 418 bool is_platform_fvp; 419 420 /*! Power domain identifier */ 421 fwk_id_t pd_id; 422 }; 423 424 /*! 425 * \brief API of the DDR PHY associated to the DMC 426 */ 427 struct mod_juno_dmc400_ddr_phy_api { 428 /*! 429 * \brief Configure the DDR PHY device. 430 * 431 * \param element_id Element identifier corresponding to the device to 432 * configure. 433 * 434 * \retval ::FWK_E_DATA No data found for the element. 435 * \retval ::FWK_SUCCESS Operation succeeded. 436 * \return One of the standard framework error codes. 437 */ 438 int (*configure_ddr)(fwk_id_t element_id); 439 440 /*! 441 * \brief Configure the clock for DDR PHY device. 442 * 443 * \param module_id Module identifier corresponding to the device to 444 * configure. 445 * 446 * \retval ::FWK_SUCCESS Operation succeeded. 447 * \return One of the standard framework error codes. 448 */ 449 int (*configure_clk)(fwk_id_t module_id); 450 451 /*! 452 * \brief Place the DDR PHY device into idle state. 453 * 454 * \param element_id Element identifier corresponding to the device to 455 * configure. 456 * 457 * \retval ::FWK_E_DATA No data found for the element. 458 * \retval ::FWK_SUCCESS Operation succeeded. 459 * \return One of the standard framework error codes. 460 */ 461 int (*configure_idle)(fwk_id_t element_id); 462 463 /*! 464 * \brief Place the DDR PHY device into retention state. 465 * 466 * \param module_id Module identifier corresponding to the device to 467 * configure. 468 * \param enable Flag to indicate the retention operation. 469 * 470 * \retval ::FWK_SUCCESS Operation succeeded. 471 * \return One of the standard framework error codes. 472 */ 473 int (*configure_retention)(fwk_id_t module_id, bool enable); 474 }; 475 476 /*! 477 * \} 478 */ 479 480 #endif /* MOD_JUNO_DMC400_H */ 481