1 /*
2 * Arm SCP/MCP Software
3 * Copyright (c) 2019-2021, Arm Limited and Contributors. All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #include "juno_mmap.h"
9
10 #include <mod_juno_ddr_phy400.h>
11
12 #include <fwk_element.h>
13 #include <fwk_id.h>
14 #include <fwk_module.h>
15 #include <fwk_module_idx.h>
16
17 static struct fwk_element juno_ddr_phy400_element_table[] = {
18 [0] = {
19 .name = "",
20 .data = &((struct mod_juno_ddr_phy400_element_config) {
21 .ddr_phy_ptm = (DDR_PHY0_BASE + OFFSET_DDR_PHY400_PTM_REGS),
22 .ddr_phy_c3a = (DDR_PHY0_BASE + OFFSET_DDR_PHY400_C3A_REGS),
23 .ddr_phy_bl0 = (DDR_PHY0_BASE + OFFSET_DDR_PHY400_BL0_REGS),
24 .ddr_phy_bl1 = (DDR_PHY0_BASE + OFFSET_DDR_PHY400_BL1_REGS),
25 .ddr_phy_bl2 = (DDR_PHY0_BASE + OFFSET_DDR_PHY400_BL2_REGS),
26 .ddr_phy_bl3 = (DDR_PHY0_BASE + OFFSET_DDR_PHY400_BL3_REGS),
27 })
28 },
29 [1] = {
30 .name = "",
31 .data = &((struct mod_juno_ddr_phy400_element_config) {
32 .ddr_phy_ptm = (DDR_PHY1_BASE + OFFSET_DDR_PHY400_PTM_REGS),
33 .ddr_phy_c3a = (DDR_PHY1_BASE + OFFSET_DDR_PHY400_C3A_REGS),
34 .ddr_phy_bl0 = (DDR_PHY1_BASE + OFFSET_DDR_PHY400_BL0_REGS),
35 .ddr_phy_bl1 = (DDR_PHY1_BASE + OFFSET_DDR_PHY400_BL1_REGS),
36 .ddr_phy_bl2 = (DDR_PHY1_BASE + OFFSET_DDR_PHY400_BL2_REGS),
37 .ddr_phy_bl3 = (DDR_PHY1_BASE + OFFSET_DDR_PHY400_BL3_REGS),
38 })
39 },
40 [2] = { 0 }, /* Termination description. */
41 };
42
juno_ddr_phy400_get_element_table(fwk_id_t module_id)43 static const struct fwk_element *juno_ddr_phy400_get_element_table
44 (fwk_id_t module_id)
45 {
46 return juno_ddr_phy400_element_table;
47 }
48
49 struct fwk_module_config config_juno_ddr_phy400 = {
50 .data =
51 &(struct mod_juno_ddr_phy400_config){
52 .timer_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_TIMER, 0),
53 },
54
55 .elements = FWK_MODULE_DYNAMIC_ELEMENTS(juno_ddr_phy400_get_element_table),
56 };
57