1 /* 2 * Arm SCP/MCP Software 3 * Copyright (c) 2020-2022, Arm Limited and Contributors. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef FMW_CMSIS_SCP_H 9 #define FMW_CMSIS_SCP_H 10 11 #include <stdint.h> 12 13 #define __CHECK_DEVICE_DEFINES 14 #define __CM7_REV 0x0000U 15 #define __FPU_PRESENT 0U 16 #define __MPU_PRESENT 1U 17 #define __ICACHE_PRESENT 0U 18 #define __DCACHE_PRESENT 0U 19 #define __DTCM_PRESENT 0U 20 #define __NVIC_PRIO_BITS 3U 21 #define __Vendor_SysTickConfig 0U 22 #define __VTOR_PRESENT 1U 23 24 #define SCP_WDOG_IRQ FWK_INTERRUPT_NMI /* SCP Watchdog (SP805) */ 25 26 extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock)*/ 27 28 typedef enum IRQn { 29 Reset_IRQn = -15, 30 NonMaskableInt_IRQn = -14, 31 HardFault_IRQn = -13, 32 MemoryManagement_IRQn = -12, 33 BusFault_IRQn = -11, 34 UsageFault_IRQn = -10, 35 SVCall_IRQn = -5, 36 DebugMonitor_IRQn = -4, 37 PendSV_IRQn = -2, 38 SysTick_IRQn = -1, 39 RESERVED0_IRQ = 0, /* Reserved */ 40 CDBG_PWR_UP_REQ_IRQ = 1, /* Coresight Debug Power Request */ 41 CSYS_PWR_UP_REQ_IRQ = 2, /* Coresight System Power Request */ 42 CDBG_RST_REQ_IRQ = 3, /* Coresight Debug Reset Request */ 43 GIC_EXT_WAKEUP_IRQ = 4, /* External GIC Wakeup Request */ 44 RESERVED5_IRQ = 5, /* Reserved */ 45 RESERVED6_IRQ = 6, /* Reserved */ 46 RESERVED7_IRQ = 7, /* Reserved */ 47 RESERVED8_IRQ = 8, /* Reserved */ 48 RESERVED9_IRQ = 9, /* Reserved */ 49 RESERVED10_IRQ = 10, /* Reserved */ 50 RESERVED11_IRQ = 11, /* Reserved */ 51 RESERVED12_IRQ = 12, /* Reserved */ 52 RESERVED13_IRQ = 13, /* Reserved */ 53 RESERVED14_IRQ = 14, /* Reserved */ 54 RESERVED15_IRQ = 15, /* Reserved */ 55 SCP_EXT_IRQ = 16, /* SCP External IRQ */ 56 GPIO_COMBINED_IRQ = 17, /* GPIO Combined IRQ */ 57 GPIO_0_IRQ = 18, /* GPIO 0 IRQ */ 58 GPIO_1_IRQ = 19, /* GPIO 1 IRQ */ 59 GPIO_2_IRQ = 20, /* GPIO 2 IRQ */ 60 GPIO_3_IRQ = 21, /* GPIO 3 IRQ */ 61 GPIO_4_IRQ = 22, /* GPIO 4 IRQ */ 62 GPIO_5_IRQ = 23, /* GPIO 5 IRQ */ 63 GPIO_6_IRQ = 24, /* GPIO 6 IRQ */ 64 GPIO_7_IRQ = 25, /* GPIO 7 IRQ */ 65 RESERVED26_IRQ = 26, /* Reserved */ 66 RESERVED27_IRQ = 27, /* Reserved */ 67 RESERVED28_IRQ = 28, /* Reserved */ 68 RESERVED29_IRQ = 29, /* Reserved */ 69 RESERVED30_IRQ = 30, /* Reserved */ 70 RESERVED31_IRQ = 31, /* Reserved */ 71 RESERVED32_IRQ = 32, /* Reserved */ 72 TIMREFCLK_IRQ = 33, /* REFCLK Physical Timer */ 73 TIMER_SYNC_IRQ = 34, /* Timer Synchronization Module */ 74 RESERVED35_IRQ = 35, /* Reserved */ 75 RESERVED36_IRQ = 36, /* Reserved */ 76 CTI_TRIGGER0_IRQ = 37, /* SCP CTI0 Trigger */ 77 CTI_TRIGGER1_IRQ = 38, /* SCP CTI1 Trigger */ 78 GIC_ERROR_ECC_IRQ = 39, /* GIC Error (ECC Fatal) */ 79 GIC_ERROR_AXIM_IRQ = 40, /* GIC Error (AXIM) */ 80 RESERVED41_IRQ = 41, /* Reserved */ 81 AON_UART_IRQ = 42, /* Always on UART */ 82 RESERVED43_IRQ = 43, /* Reserved */ 83 GEN_WD_WS0_IRQ = 44, /* Generic Watchdog timer WS0 */ 84 GEN_WD_WS1_IRQ = 45, /* Generic Watchdog timer WS1 */ 85 TRUSTED_WD_WS0_IRQ = 46, /* Trusted Watchdog timer WS0 */ 86 TRUSTED_WD_WS1_IRQ = 47, /* Trusted Watchdog timer WS1 */ 87 APPS_UART_IRQ = 48, /* Application UART */ 88 RESERVED49_IRQ = 49, /* Reserved */ 89 PPU_CORES0_IRQ = 50, /* Consolidated PPU Interrupt for 90 cores 1-32, 129-160 */ 91 PPU_CORES1_IRQ = 51, /* Consolidated PPU Interrupt for 92 cores 33-64, 161-192 */ 93 PPU_CORES2_IRQ = 52, /* Consolidated PPU Interrupt for 94 cores 65-96, 193-224 */ 95 PPU_CORES3_IRQ = 53, /* Consolidated PPU Interrupt for 96 cores 97-128, 225-256 */ 97 PPU_CLUSTERS_IRQ = 54, /* Consolidated clusters PPU */ 98 PLL_CORES0_LOCK_IRQ = 55, /* Consolidated PLL lock for PLLs 99 1-32, 65-96, 129-160, 193-224 */ 100 PLL_CORES1_LOCK_IRQ = 56, /* Consolidated PLL lock for PLLs 101 33-64, 97-128, 161-192, 225-256 */ 102 PLL_CORES0_UNLOCK_IRQ = 57, /* Consolidated PLL unlock for PLLs 103 1-32, 65-96, 129-160, 193-224 */ 104 PLL_CORES1_UNLOCK_IRQ = 58, /* Consolidated PLL lock for PLLs 105 33-64, 97-128, 161-192, 225-256 */ 106 FAULT_CORES_IRQ = 59, /* Consolidated fault IRQ for 107 cores */ 108 RESERVED60_IRQ = 60, /* Reserved */ 109 RESERVED61_IRQ = 61, /* Reserved */ 110 RESERVED62_IRQ = 62, /* Reserved */ 111 RESERVED63_IRQ = 63, /* Reserved */ 112 ECC_CORES_ERROR_IRQ = 64, /* Consolidated ECC ERROR for 113 cores */ 114 RESERVED65_IRQ = 65, /* Reserved */ 115 RESERVED66_IRQ = 66, /* Reserved */ 116 RESERVED67_IRQ = 67, /* Reserved */ 117 RESERVED68_IRQ = 68, /* Reserved */ 118 PLL_CLUSTERS_LOCK_IRQ = 69, /* Consolidated clusters PLL Lock */ 119 PLL_CLUSTERS_UNLOCK_IRQ = 70, /* Consolidated clusters PLL Unlock*/ 120 RESERVED71_IRQ = 71, /* Reserved */ 121 RESERVED72_IRQ = 72, /* Reserved */ 122 RESERVED73_IRQ = 73, /* Reserved */ 123 RESERVED74_IRQ = 74, /* Reserved */ 124 RESERVED75_IRQ = 75, /* Reserved */ 125 RESERVED76_IRQ = 76, /* Reserved */ 126 RESERVED77_IRQ = 77, /* Reserved */ 127 RESERVED78_IRQ = 78, /* Reserved */ 128 RESERVED79_IRQ = 79, /* Reserved */ 129 RESERVED80_IRQ = 80, /* Reserved */ 130 RESERVED81_IRQ = 81, /* Reserved */ 131 MHU_AP_NONSEC_IRQ = 82, /* MHU non-secure irq bewteen SCP and 132 AP */ 133 MHU_AP_SEC_IRQ = 83, /* MHU secure irq bewteen SCP and 134 AP */ 135 MHU_MCP_NONSEC_IRQ = 84, /* MHU non-secure irq between SCP and 136 MCP */ 137 MHU_MCP_SEC_IRQ = 85, /* MHU secure irq bewteen SCP and 138 MCP */ 139 RESERVED86_IRQ = 86, /* Reserved */ 140 RESERVED87_IRQ = 87, /* Reserved */ 141 RESERVED88_IRQ = 88, /* Reserved */ 142 RESERVED89_IRQ = 89, /* Reserved */ 143 TIMER_CLUSTERS_IRQ = 90, /* Consolidated clusters timer 144 interrupt */ 145 RESERVED91_IRQ = 91, /* Reserved */ 146 RESERVED92_IRQ = 92, /* Reserved */ 147 RESERVED93_IRQ = 93, /* Reserved */ 148 MMU_TCU_RASIRPT_IRQ = 94, /* Consolidated MMU RAS */ 149 MMU_TBU_RASIRPT_IRQ = 95, /* Consolidated TBU RAS */ 150 INT_PPU_IRQ = 96, /* PPU interrupt from Interconnect 151 PPU */ 152 INT_ERRNS_IRQ = 97, /* Non-Sec error interrupt from 153 Interconnect PPU */ 154 INT_ERRS_IRQ = 98, /* Secure error interrupt from 155 Interconnect PPU */ 156 INT_FAULTS_IRQ = 99, /* Secure fault interrupt from 157 Interconnect PPU */ 158 INT_FAULTNS_IRQ = 100, /* Non-Sec fault interrupt from 159 Interconnect PPU */ 160 INT_PMU_DTC_GT_0_IRQ = 101, /* PMU count overflow irq 161 if #DTC > 0 */ 162 INT_PMU_DTC_GT_1_IRQ = 102, /* PMU count overflow irq 163 if #DTC > 1 */ 164 INT_PMU_DTC_GT_2_IRQ = 103, /* PMU count overflow irq 165 if #DTC > 2 */ 166 INT_PMU_DTC_GT_3_IRQ = 104, /* PMU count overflow irq 167 if #DTC > 3 */ 168 RESERVED105_IRQ = 105, /* Reserved */ 169 RESERVED106_IRQ = 106, /* Reserved */ 170 RESERVED107_IRQ = 107, /* Reserved */ 171 RESERVED108_IRQ = 108, /* Reserved */ 172 RESERVED109_IRQ = 109, /* Reserved */ 173 RESERVED110_IRQ = 110, /* Reserved */ 174 RESERVED111_IRQ = 111, /* Reserved */ 175 RESERVED112_IRQ = 112, /* Reserved */ 176 RESERVED113_IRQ = 113, /* Reserved */ 177 RESERVED114_IRQ = 114, /* Reserved */ 178 RESERVED115_IRQ = 115, /* Reserved */ 179 RESERVED116_IRQ = 116, /* Reserved */ 180 RESERVED117_IRQ = 117, /* Reserved */ 181 RESERVED118_IRQ = 118, /* Reserved */ 182 RESERVED119_IRQ = 119, /* Reserved */ 183 RESERVED120_IRQ = 120, /* Reserved */ 184 RESERVED121_IRQ = 121, /* Reserved */ 185 RESERVED122_IRQ = 122, /* Reserved */ 186 RESERVED123_IRQ = 123, /* Reserved */ 187 RESERVED124_IRQ = 124, /* Reserved */ 188 RESERVED125_IRQ = 125, /* Reserved */ 189 RESERVED126_IRQ = 126, /* Reserved */ 190 RESERVED127_IRQ = 127, /* Reserved */ 191 RESERVED128_IRQ = 128, /* Reserved */ 192 RESERVED129_IRQ = 129, /* Reserved */ 193 DEBUG_PIK_IRQ = 130, /* DEBUG PIK */ 194 PPU_LOGIC_IRQ = 131, /* PPU LOGIC */ 195 RESERVED132_IRQ = 132, /* Reserved */ 196 RESERVED133_IRQ = 133, /* Reserved */ 197 RESERVED134_IRQ = 134, /* Reserved */ 198 PPU_SRAM_IRQ = 135, /* PPU SRAM */ 199 PPU_DPU_IRQ = 136, /* PPU DPU */ 200 PPU_GPU_IRQ = 137, /* PPU GPU */ 201 RESERVED138_IRQ = 138, /* Reserved */ 202 MCP_WD_WS1_IRQ = 139, /* MCP watchdog reset */ 203 PLL_SYS_LOCK_IRQ = 140, /* System PLL Lock */ 204 PLL_SYS_UNLOCK_IRQ = 141, /* System PLL Unlock */ 205 PLL_INT_LOCK_IRQ = 142, /* Interconnect PLL Lock */ 206 PLL_INT_UNLOCK_IRQ = 143, /* Interconnect PLL Unlock */ 207 PLL_DPU_LOCK_IRQ = 144, /* DPU PLL Lock */ 208 PLL_DPU_UNLOCK_IRQ = 145, /* DPU PLL Unlock */ 209 PLL_GPU_LOCK_IRQ = 146, /* GPU PLL Lock */ 210 PLL_GPU_UNLOCK_IRQ = 147, /* GPU PLL Unlock */ 211 PLL_PXL_LOCK_IRQ = 148, /* PXL PLL Lock */ 212 PLL_PXL_UNLOCK_IRQ = 149, /* PXL PLL Unlock */ 213 RESERVED150_IRQ = 150, /* Reserved */ 214 RESERVED151_IRQ = 151, /* Reserved */ 215 RESERVED152_IRQ = 152, /* Reserved */ 216 RESERVED153_IRQ = 153, /* Reserved */ 217 RESERVED154_IRQ = 154, /* Reserved */ 218 RESERVED155_IRQ = 155, /* Reserved */ 219 RESERVED156_IRQ = 156, /* Reserved */ 220 RESERVED157_IRQ = 157, /* Reserved */ 221 RESERVED158_IRQ = 158, /* Reserved */ 222 RESERVED159_IRQ = 159, /* Reserved */ 223 RESERVED160_IRQ = 160, /* Reserved */ 224 RESERVED161_IRQ = 161, /* Reserved */ 225 RESERVED162_IRQ = 162, /* Reserved */ 226 RESERVED163_IRQ = 163, /* Reserved */ 227 RESERVED164_IRQ = 164, /* Reserved */ 228 RESERVED165_IRQ = 165, /* Reserved */ 229 RESERVED166_IRQ = 166, /* Reserved */ 230 RESERVED167_IRQ = 167, /* Reserved */ 231 RESERVED168_IRQ = 168, /* Reserved */ 232 RESERVED169_IRQ = 169, /* Reserved */ 233 RESERVED170_IRQ = 170, /* Reserved */ 234 RESERVED171_IRQ = 171, /* Reserved */ 235 RESERVED172_IRQ = 172, /* Reserved */ 236 RESERVED173_IRQ = 173, /* Reserved */ 237 PLL_DMC_LOCK_IRQ = 174, /* DMC PLL LOCK */ 238 PLL_DMC_UNLOCK_IRQ = 175, /* DMC PLL LOCK */ 239 RESERVED176_IRQ = 176, /* Reserved */ 240 RESERVED177_IRQ = 177, /* Reserved */ 241 RESERVED178_IRQ = 178, /* Reserved */ 242 RESERVED179_IRQ = 179, /* Reserved */ 243 DMCS0_MISC_OFLOW_IRQ = 180, /* DMC 0/4 Combined Misc Overflow */ 244 DMCS0_ERR_OFLOW_IRQ = 181, /* DMC 0/4 Error Overflow */ 245 DMCS0_ECC_ERR_INT_IRQ = 182, /* DMC 0/4 ECC Error Int */ 246 DMCS0_MISC_ACCESS_INT_IRQ = 183, /* DMC 0/4 Combined Miscellaneous 247 access int */ 248 DMCS0_TEMPERATURE_EVENT_INT_IRQ = 184, /* DMC 0/4 Temperature event int */ 249 DMCS0_FAILED_ACCESS_INT_IRQ = 185, /* DMC 0/4 Failed access int */ 250 DMCS0_MGR_INT_IRQ = 186, /* DMC 0/4 combined manager int */ 251 DMCS1_MISC_OFLOW_IRQ = 187, /* DMC 1/5 Combined Misc Overflow */ 252 DMCS1_ERR_OFLOW_IRQ = 188, /* DMC 1/5 Error Overflow */ 253 DMCS1_ECC_ERR_INT_IRQ = 189, /* DMC 1/5 ECC Error Int */ 254 DMCS1_MISC_ACCESS_INT_IRQ = 190, /* DMC 1/5 Combined Miscellaneous 255 access int */ 256 DMCS1_TEMPERATURE_EVENT_INT_IRQ = 191, /* DMC 1/5 Temperature event int */ 257 DMCS1_FAILED_ACCESS_INT_IRQ = 192, /* DMC 1/5 Failed access int */ 258 DMCS1_MGR_INT_IRQ = 193, /* DMC 1/5 combined manager int */ 259 DMCS2_MISC_OFLOW_IRQ = 194, /* DMC 2/6 Combined Misc Overflow */ 260 DMCS2_ERR_OFLOW_IRQ = 195, /* DMC 2/6 Error Overflow */ 261 DMCS2_ECC_ERR_INT_IRQ = 196, /* DMC 2/6 ECC Error Int */ 262 DMCS2_MISC_ACCESS_INT_IRQ = 197, /* DMC 2/6 Combined Miscellaneous 263 access int */ 264 DMCS2_TEMPERATURE_EVENT_INT_IRQ = 198, /* DMC 2/6 Temperature event int */ 265 DMCS2_FAILED_ACCESS_INT_IRQ = 199, /* DMC 2/6 Failed access int */ 266 DMCS2_MGR_INT_IRQ = 200, /* DMC 2/6 combined manager int */ 267 DMCS3_MISC_OFLOW_IRQ = 201, /* DMC 3/7 Combined Misc Overflow */ 268 DMCS3_ERR_OFLOW_IRQ = 202, /* DMC 3/7 Error Overflow */ 269 DMCS3_ECC_ERR_INT_IRQ = 203, /* DMC 3/7 ECC Error Int */ 270 DMCS3_MISC_ACCESS_INT_IRQ = 204, /* DMC 3/7 Combined Miscellaneous 271 access int */ 272 DMCS3_TEMPERATURE_EVENT_INT_IRQ = 205, /* DMC 3/7 Temperature event int */ 273 DMCS3_FAILED_ACCESS_INT_IRQ = 206, /* DMC 3/7 Failed access int */ 274 DMCS3_MGR_INT_IRQ = 207, /* DMC 3/7 combined manager int */ 275 SCP_I2C0_IRQ = 208, /* SCP C2C I2C interrupt */ 276 SCP_I2C1_IRQ = 209, /* SCP PMIC I2C interrupt */ 277 SCP_I2C2_IRQ = 210, /* SCP SPD-PCC I2C interrupt */ 278 SCP_QSPI_IRQ = 211, /* SCP QSPI interrupt */ 279 SCP_PVT_IRQ = 212, /* SCP PVT Controller interrupt */ 280 RESERVED213_IRQ = 213, /* Reserved */ 281 RESERVED214_IRQ = 214, /* Reserved */ 282 RESERVED215_IRQ = 215, /* Reserved */ 283 RESERVED216_IRQ = 216, /* Reserved */ 284 RESERVED217_IRQ = 217, /* Reserved */ 285 RESERVED218_IRQ = 218, /* Reserved */ 286 CCIX_BUS_DEV_CHG_IRQ = 219, /* CCIX Bus Device Change 287 interrupt */ 288 CCIX_INTA_OUT_IRQ = 220, /* CCIX INTA Out interrupt */ 289 CCIX_INTB_OUT_IRQ = 221, /* CCIX INTB Out interrupt */ 290 CCIX_INTC_OUT_IRQ = 222, /* CCIX INTC Out interrupt */ 291 CCIX_INTD_OUT_IRQ = 223, /* CCIX INTD Out interrupt */ 292 CCIX_PHY_INT_OUT_IRQ = 224, /* CCIX phy interrupt out 293 interrupt */ 294 CCIX_AER_IRQ = 225, /* CCIX address enable interrupt */ 295 CCIX_LINK_DOWN_RESET_IRQ = 226, /* CCIX link down reset interrupt */ 296 CCIX_LOCAL_INT_REST_IRQ = 227, /* CCIX local error & status 297 interrupt */ 298 CCIX_PERF_DATA_THRESHOLD_IRQ = 228, /* CCIX performance data threshold 299 interrupt */ 300 CCIX_NEG_SPD_CHANGE_IRQ = 229, /* CCIX nogotiated speed change 301 interrupt */ 302 CCIX_LINK_TRAIN_DONE_IRQ = 230, /* CCIX link training done 303 interrupt */ 304 CCIX_PLL_STATUS_RISE_IRQ = 231, /* CCIX PLL status rise interrupt */ 305 CCIX_MSG_FIFO_IRQ = 232, /* CCIX message FIFO interrupt */ 306 CCIX_LOCAL_INT_RAS_IRQ = 233, /* CCIX local RAS interrupt */ 307 CCIX_HOT_RESET_IRQ = 234, /* CCIX hot reset interrupt */ 308 CCIX_FLR_RST_IRQ = 235, /* CCIX function level reset 309 interrupt */ 310 CCIX_PWR_STATE_CHANGE_IRQ = 236, /* CCIX power state change 311 interrupt */ 312 PCIE_AER_IRQ = 237, /* PCIe address enable interrupt */ 313 PCIE_LOCAL_INT_REST_IRQ = 238, /* PCIe local error & status 314 interrupt */ 315 PCIE_LOCAL_INT_RAS_IRQ = 239, /* PCIe local RAS interrupt */ 316 317 IRQn_MAX = INT16_MAX, 318 } IRQn_Type; 319 320 #include <core_cm7.h> 321 322 #endif /* FMW_CMSIS_SCP_H */ 323