1 /* 2 * Arm SCP/MCP Software 3 * Copyright (c) 2020-2021, Arm Limited and Contributors. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef MORELLO_PIK_CPU_H 9 #define MORELLO_PIK_CPU_H 10 11 #include <fwk_macros.h> 12 13 #include <stdint.h> 14 15 #define PE_COUNT_MAX 16 16 17 /*! 18 * \brief PE Static Configuration register definitions 19 */ 20 struct static_config_reg { 21 FWK_RW uint32_t STATIC_CONFIG; 22 FWK_RW uint32_t RVBARADDR_LW; 23 FWK_RW uint32_t RVBARADDR_UP; 24 uint32_t RESERVED; 25 }; 26 27 /*! 28 * \brief AP cores clock control register definitions 29 */ 30 struct coreclk_reg { 31 FWK_RW uint32_t CTRL; 32 FWK_RW uint32_t DIV; 33 uint32_t RESERVED; 34 FWK_RW uint32_t MOD; 35 }; 36 37 /*! 38 * \brief CPU (V8.2) PIK register definitions 39 */ 40 struct pik_cpu_reg { 41 FWK_RW uint32_t CLUSTER_CONFIG; 42 uint8_t RESERVED0[0x10 - 0x4]; 43 struct static_config_reg STATIC_CONFIG[PE_COUNT_MAX]; 44 uint8_t RESERVED1[0x800 - 0x110]; 45 FWK_RW uint32_t PPUCLK_CTRL; 46 FWK_RW uint32_t PPUCLK_DIV1; 47 uint8_t RESERVED2[0x810 - 0x808]; 48 FWK_RW uint32_t PCLK_CTRL; 49 uint8_t RESERVED3[0x820 - 0x814]; 50 FWK_RW uint32_t ATCLK_CTRL; 51 uint8_t RESERVED4[0x830 - 0x824]; 52 FWK_RW uint32_t GICCLK_CTRL; 53 uint8_t RESERVED5[0x840 - 0x834]; 54 FWK_RW uint32_t AMBACLK_CTRL; 55 uint8_t RESERVED6[0x850 - 0x844]; 56 FWK_RW uint32_t CLUSCLK_CTRL; 57 FWK_RW uint32_t CLUSCLK_DIV1; 58 uint8_t RESERVED7[0x860 - 0x858]; 59 struct coreclk_reg CORECLK[8]; 60 uint8_t RESERVED8[0xA00 - 0x8E0]; 61 FWK_R uint32_t CLKFORCE_STATUS; 62 FWK_RW uint32_t CLKFORCE_SET; 63 FWK_RW uint32_t CLKFORCE_CLR; 64 uint8_t RESERVED9[0xFB8 - 0xA0C]; 65 FWK_R uint32_t CAP2; 66 FWK_R uint32_t CAP; 67 FWK_R uint32_t PIK_CONFIG; 68 FWK_R uint8_t RESERVED10[0xFD0 - 0xFC4]; 69 FWK_R uint32_t PID4; 70 FWK_R uint32_t PID5; 71 FWK_R uint32_t PID6; 72 FWK_R uint32_t PID7; 73 FWK_R uint32_t PID0; 74 FWK_R uint32_t PID1; 75 FWK_R uint32_t PID2; 76 FWK_R uint32_t PID3; 77 FWK_R uint32_t ID0; 78 FWK_R uint32_t ID1; 79 FWK_R uint32_t ID2; 80 FWK_R uint32_t ID3; 81 }; 82 83 #define PIK_CPU_CAP_CLUSSYNC UINT32_C(0x00000001) 84 #define PIK_CPU_CAP_CORESYNC(CORE) ((uint32_t)(1 << ((CORE) + 1))) 85 #define PIK_CPU_CAP_PE_MASK UINT32_C(0xF0000000) 86 #define PIK_CPU_CAP_PE_POS 28 87 88 #endif /* MORELLO_PIK_CPU_H */ 89