1 /*
2  * Arm SCP/MCP Software
3  * Copyright (c) 2020-2021, Arm Limited and Contributors. All rights reserved.
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  *
7  * Description:
8  *     MCP PIK registers
9  */
10 
11 #ifndef MORELLO_PIK_MCP_H
12 #define MORELLO_PIK_MCP_H
13 
14 #include <fwk_macros.h>
15 
16 #include <stdint.h>
17 
18 /*!
19  * \brief MCP PIK register definitions
20  */
21 struct pik_mcp_reg {
22     uint8_t RESERVED0[0x10 - 0x0];
23     FWK_RW uint32_t RESET_SYNDROME;
24     uint8_t RESERVED1[0x20 - 0x14];
25     FWK_RW uint32_t SURVIVAL_RESET_STATUS;
26     uint8_t RESERVED2[0x34 - 0x24];
27     FWK_RW uint32_t ADDR_TRANS;
28     FWK_RW uint32_t DBG_ADDR_TRANS;
29     uint8_t RESERVED3[0x40 - 0x3C];
30     FWK_RW uint32_t WS1_TIMER_MATCH;
31     FWK_RW uint32_t WS1_TIMER_EN;
32     uint8_t RESERVED4[0x200 - 0x48];
33     FWK_R uint32_t SS_RESET_STATUS;
34     FWK_W uint32_t SS_RESET_SET;
35     FWK_W uint32_t SS_RESET_CLR;
36     uint8_t RESERVED5[0x810 - 0x20C];
37     FWK_RW uint32_t CORECLK_CTRL;
38     FWK_RW uint32_t CORECLK_DIV1;
39     uint8_t RESERVED6[0x820 - 0x818];
40     FWK_RW uint32_t ACLK_CTRL;
41     FWK_RW uint32_t ACLK_DIV1;
42     uint8_t RESERVED7[0xA10 - 0x828];
43     FWK_R uint32_t PLL_STATUS0;
44     uint8_t RESERVED8[0xFC0 - 0xA14];
45     FWK_R uint32_t PWR_CTRL_CONFIG;
46     uint8_t RESERVED18[0xFD0 - 0xFC4];
47     FWK_R uint32_t PID4;
48     FWK_R uint32_t PID5;
49     FWK_R uint32_t PID6;
50     FWK_R uint32_t PID7;
51     FWK_R uint32_t PID0;
52     FWK_R uint32_t PID1;
53     FWK_R uint32_t PID2;
54     FWK_R uint32_t PID3;
55     FWK_R uint32_t ID0;
56     FWK_R uint32_t ID1;
57     FWK_R uint32_t ID2;
58     FWK_R uint32_t ID3;
59 };
60 
61 #endif /* MORELLO_PIK_MCP_H */
62