1 /* 2 * Arm SCP/MCP Software 3 * Copyright (c) 2020-2021, Arm Limited and Contributors. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 * 7 * Description: 8 * System Configuration Controller (SCC) registers. 9 */ 10 11 #ifndef MORELLO_SCC_REG_H 12 #define MORELLO_SCC_REG_H 13 14 #include <fwk_macros.h> 15 16 #include <stdint.h> 17 18 struct scc_pcid_registers { 19 FWK_R uint32_t PID4; 20 FWK_R uint32_t PID0; 21 FWK_R uint32_t PID1; 22 FWK_R uint32_t PID2; 23 FWK_R uint32_t PID3; 24 FWK_R uint32_t CID0; 25 FWK_R uint32_t CID1; 26 FWK_R uint32_t CID2; 27 FWK_R uint32_t CID3; 28 }; 29 30 struct scc_reg { 31 uint32_t RESERVED0; 32 FWK_RW uint32_t PMCLK_DIV; 33 uint32_t RESERVED1; 34 FWK_RW uint32_t SYSAPBCLK_CTRL; 35 FWK_RW uint32_t SYSAPBCLK_DIV; 36 uint32_t RESERVED2; 37 FWK_RW uint32_t IOFPGA_TMIF2XCLK_CTRL; 38 FWK_RW uint32_t IOFPGA_TMIF2XCLK_DIV; 39 uint32_t RESERVED3; 40 FWK_RW uint32_t IOFPGA_TSIF2XCLK_CTRL; 41 FWK_RW uint32_t IOFPGA_TSIF2XCLK_DIV; 42 uint32_t RESERVED4; 43 FWK_RW uint32_t SCPNICCLK_CTRL; 44 FWK_RW uint32_t SCPNICCLK_DIV; 45 uint32_t RESERVED5; 46 FWK_RW uint32_t SCPI2CCLK_CTRL; 47 FWK_RW uint32_t SCPI2CCLK_DIV; 48 uint32_t RESERVED6; 49 FWK_RW uint32_t SCPQSPICLK_CTRL; 50 FWK_RW uint32_t SCPQSPICLK_DIV; 51 uint32_t RESERVED7; 52 FWK_RW uint32_t SENSORCLK_CTRL; 53 FWK_RW uint32_t SENSORCLK_DIV; 54 uint32_t RESERVED8; 55 FWK_RW uint32_t MCPNICCLK_CTRL; 56 FWK_RW uint32_t MCPNICCLK_DIV; 57 uint32_t RESERVED9; 58 FWK_RW uint32_t MCPI2CCLK_CTRL; 59 FWK_RW uint32_t MCPI2CCLK_DIV; 60 uint32_t RESERVED10; 61 FWK_RW uint32_t MCPQSPICLK_CTRL; 62 FWK_RW uint32_t MCPQSPICLK_DIV; 63 uint32_t RESERVED11; 64 FWK_RW uint32_t PCIEAXICLK_CTRL; 65 FWK_RW uint32_t PCIEAXICLK_DIV; 66 uint32_t RESERVED12; 67 FWK_RW uint32_t CCIXAXICLK_CTRL; 68 FWK_RW uint32_t CCIXAXICLK_DIV; 69 uint32_t RESERVED13; 70 FWK_RW uint32_t PCIEAPBCLK_CTRL; 71 FWK_RW uint32_t PCIEAPBCLK_DIV; 72 uint32_t RESERVED14; 73 FWK_RW uint32_t CCIXAPBCLK_CTRL; 74 FWK_RW uint32_t CCIXAPBCLK_DIV; 75 uint8_t RESERVED15[0xF0 - 0xB0]; 76 FWK_RW uint32_t SYS_CLK_EN; 77 uint8_t RESERVED16[0x100 - 0xF4]; 78 79 /* PLL Control Registers */ 80 FWK_RW uint32_t CPU0_PLL_CTRL0; 81 FWK_RW uint32_t CPU0_PLL_CTRL1; 82 FWK_RW uint32_t CPU1_PLL_CTRL0; 83 FWK_RW uint32_t CPU1_PLL_CTRL1; 84 FWK_RW uint32_t CLUS_PLL_CTRL0; 85 FWK_RW uint32_t CLUS_PLL_CTRL1; 86 FWK_RW uint32_t SYS_PLL_CTRL0; 87 FWK_RW uint32_t SYS_PLL_CTRL1; 88 FWK_RW uint32_t DMC_PLL_CTRL0; 89 FWK_RW uint32_t DMC_PLL_CTRL1; 90 FWK_RW uint32_t INT_PLL_CTRL0; 91 FWK_RW uint32_t INT_PLL_CTRL1; 92 FWK_RW uint32_t GPU_PLL_CTRL0; 93 FWK_RW uint32_t GPU_PLL_CTRL1; 94 FWK_RW uint32_t DPU_PLL_CTRL0; 95 FWK_RW uint32_t DPU_PLL_CTRL1; 96 FWK_RW uint32_t PXL_PLL_CTRL0; 97 FWK_RW uint32_t PXL_PLL_CTRL1; 98 uint8_t RESERVED17[0x150 - 0x148]; 99 100 /* Reset Control Registers */ 101 FWK_RW uint32_t SYS_MAN_RESET; 102 uint8_t RESERVED18[0x160 - 0x154]; 103 104 /* Boot Control Registers */ 105 FWK_RW uint32_t BOOT_CTRL; 106 FWK_RW uint32_t BOOT_CTRL_STA; 107 FWK_RW uint32_t SCP_BOOT_ADR; 108 FWK_RW uint32_t MCP_BOOT_ADR; 109 FWK_RW uint32_t PLATFORM_CTRL; 110 FWK_RW uint32_t TARGET_ID_APP; 111 FWK_RW uint32_t TARGET_ID_SCP; 112 FWK_RW uint32_t TARGET_ID_MCP; 113 FWK_RW uint32_t BOOT_GPR0; 114 FWK_RW uint32_t BOOT_GPR1; 115 FWK_RW uint32_t BOOT_GPR2; 116 FWK_RW uint32_t BOOT_GPR3; 117 FWK_RW uint32_t BOOT_GPR4; 118 FWK_RW uint32_t BOOT_GPR5; 119 FWK_RW uint32_t BOOT_GPR6; 120 FWK_RW uint32_t BOOT_GPR7; 121 FWK_RW uint32_t INSTANCE_ID; 122 FWK_RW uint32_t PCIE_BOOT_CTRL; 123 FWK_RW uint32_t MISC_BOOT_CTRL; 124 FWK_RW uint32_t GPU_CTRL; 125 126 /* Component Control Registers */ 127 FWK_RW uint32_t TEST_MUX_CTRL; 128 FWK_RW uint32_t DBG_AUTHN_CTRL; 129 FWK_RW uint32_t CTI0_CTRL; 130 FWK_RW uint32_t CTI1_CTRL; 131 FWK_RW uint32_t CTI0TO3_CTRL; 132 FWK_RW uint32_t MCP_WDOGCTI_CTRL; 133 FWK_RW uint32_t SCP_WDOGCTI_CTRL; 134 FWK_RW uint32_t DBGEXPCTI_CTRL; 135 FWK_RW uint32_t PCIE_PM_CTRL; 136 FWK_RW uint32_t CCIX_PM_CTRL; 137 FWK_RW uint32_t SCDBG_CTRL; 138 FWK_RW uint32_t EXP_IF_CTRL; 139 FWK_RW uint32_t PCIE_TEST_MUX_CTRL; 140 FWK_RW uint32_t RO_CTRL; 141 FWK_RW uint32_t CMN_CCIX_CTRL; 142 FWK_RW uint32_t STM_CTRL; 143 FWK_RW uint32_t AXI_OVRD_PCIE; 144 FWK_RW uint32_t AXI_OVRD_CCIX; 145 FWK_RW uint32_t AXI_OVRD_TSIF; 146 FWK_RW uint32_t GPU_TEXFMTENABLE; 147 148 /* Pad Control Registers */ 149 FWK_RW uint32_t TRACE_PAD_CTRL0; 150 FWK_RW uint32_t TRACE_PAD_CTRL1; 151 FWK_RW uint32_t IOFPGA_TMIF_PAD_CTRL; 152 FWK_RW uint32_t IOFPGA_TSIF_PAD_CTRL; 153 FWK_RW uint32_t DISPLAY_PAD_CTRL0; 154 FWK_RW uint32_t DISPLAY_PAD_CTRL1; 155 uint8_t RESERVED21[0x260 - 0x218]; 156 157 /* EMA Registers */ 158 FWK_RW uint32_t CPU0_FCISRAMSPUHD_EMA_CTRL; 159 FWK_RW uint32_t CPU0_CORINTH_FCIRFSPHD_HS_EMA_CTRL; 160 uint32_t RESERVED22; 161 FWK_RW uint32_t CPU0_FCIRFSPHD_EMA_CTRL; 162 FWK_RW uint32_t CPU0_RFSPHDS_EMA_CTRL; 163 FWK_RW uint32_t CPU0_FCIRF2PHS_EMA_CTRL; 164 FWK_RW uint32_t CPU1_FCISRAMSPUHD_EMA_CTRL; 165 FWK_RW uint32_t CPU1_CORINTH_FCIRFSPHD_HS_EMA_CTRL; 166 uint32_t RESERVED23; 167 FWK_RW uint32_t CPU1_FCIRFSPHD_EMA_CTRL; 168 FWK_RW uint32_t CPU1_RFSPHDS_EMA_CTRL; 169 FWK_RW uint32_t CPU1_FCIRF2PHS_EMA_CTRL; 170 FWK_RW uint32_t CPU0_CORINTH_FCIRF2PHS_EMA_CTRL; 171 FWK_RW uint32_t CPU0_CORINTH_FCISRAMSPUHD_EMA_CTRL; 172 FWK_RW uint32_t CPU0_CORINTH_FCIRFSPHD_ARES_EMA_CTRL; 173 FWK_RW uint32_t CPU0_CORINTH_FCIRFSPHD_EMA_CTRL; 174 FWK_RW uint32_t CPU0_CORINTH_RFSPHDS_EMA_CTRL; 175 FWK_RW uint32_t CPU1_CORINTH_FCIRF2PHS_EMA_CTRL; 176 FWK_RW uint32_t CPU1_CORINTH_FCISRAMSPUHD_EMA_CTRL; 177 FWK_RW uint32_t CPU1_CORINTH_FCIRFSPHD_ARES_EMA_CTRL; 178 FWK_RW uint32_t CPU1_CORINTH_FCIRFSPHD_EMA_CTRL; 179 FWK_RW uint32_t CPU1_CORINTH_RFSPHDS_EMA_CTRL; 180 FWK_RW uint32_t DMC_RFSPHDE_EMA_CTRL; 181 FWK_RW uint32_t DEBUG_SRAMSPHDE_EMA_CTRL; 182 FWK_RW uint32_t MSCP_RFSPHDE_EMA_CTRL; 183 FWK_RW uint32_t MSCP_SRAMSPHDE_EMA_CTRL; 184 FWK_RW uint32_t MSCP_ROM_EMA_CTRL; 185 FWK_RW uint32_t MMU_RFSPHDE_EMA_CTRL; 186 FWK_RW uint32_t BASE_SRAMSPHDE_EMA_CTRL; 187 FWK_RW uint32_t BASE_ROM_EMA_CTRL; 188 uint32_t RESERVED24; 189 uint32_t RESERVED25; 190 FWK_RW uint32_t GIC_RFSPHDE_EMA_CTRL; 191 FWK_RW uint32_t PCIE_RFSPHDE_EMA_CTRL; 192 FWK_RW uint32_t PCIE_RF2PHSC_EMA_CTRL; 193 FWK_RW uint32_t CCIX_RFSPHDE_EMA_CTRL; 194 FWK_RW uint32_t CCIX_RF2PHSC_EMA_CTRL; 195 FWK_RW uint32_t POR_RF2PHSC_EMA_CTRL; 196 FWK_RW uint32_t POR_FCISRAMSPUHD_FCM_EMA_CTRL; 197 FWK_RW uint32_t POR_FCIRFSPHD_FCM_EMA_CTRL; 198 FWK_RW uint32_t DPU_FCIRFSPHD_EMA_CTRL; 199 FWK_RW uint32_t DPU_RFSPHDE_EMA_CTRL; 200 FWK_RW uint32_t DPU_RF2PHSC_EMA_CTRL; 201 FWK_RW uint32_t DPU_SRAMSPHDE_EMA_CTRL; 202 FWK_RW uint32_t DPU_SRAM2PUHDE_EMA_CTRL; 203 FWK_RW uint32_t GPU_RFSPHDE_EMA_CTRL; 204 FWK_RW uint32_t GPU_RF2PHSC_EMA_CTRL; 205 FWK_RW uint32_t GPU_SRAMSPHDE_EMA_CTRL; 206 FWK_RW uint32_t GPU_SRAM2PUHDE_EMA_CTRL; 207 FWK_RW uint32_t MMU_FCIRFSPHD_FCM_EMA_CTRL; 208 uint8_t RESERVED26[0xE00 - 0x328]; 209 210 /* APB Magic Registers */ 211 FWK_RW uint32_t APB_CTRL_CLR; 212 uint8_t RESERVED27[0xFD0 - 0xE04]; 213 214 /* PID/CID Magic Registers */ 215 const struct scc_pcid_registers PCID; 216 }; 217 218 #define SCC_PLATFORM_CTRL_MULTI_CHIP_MODE_POS 8 219 #define SCC_PLATFORM_CTRL_CHIPID_POS 0 220 221 #define SCC_PLATFORM_CTRL_MULTI_CHIP_MODE_MASK \ 222 (UINT32_C(0x1) << SCC_PLATFORM_CTRL_MULTI_CHIP_MODE_POS) 223 #define SCC_PLATFORM_CTRL_CHIPID_MASK \ 224 (UINT32_C(0x3F) << SCC_PLATFORM_CTRL_CHIPID_POS) 225 226 #define SCC_CCIX_PM_CTRL_PWR_REQ_POS UINT32_C(1) 227 #define SCC_PCIE_PM_CTRL_PWR_REQ_POS UINT32_C(1) 228 229 #define SCC_CCIX_PM_CTRL_PWR_ACK_MASK UINT32_C(0x2) 230 #define SCC_PCIE_PM_CTRL_PWR_ACK_MASK UINT32_C(0x2) 231 232 #define SCC_SYS_MAN_RESET_CCIX_POS UINT32_C(11) 233 #define SCC_SYS_MAN_RESET_PCIE_POS UINT32_C(10) 234 235 #define SCC_BOOTGPR1_L3_CACHE_EN_MASK UINT32_C(0x10) 236 #endif /* MORELLO_SCC_REG_H */ 237