1 /*
2 * Arm SCP/MCP Software
3 * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #include <config_clock.h>
9 #include <config_power_domain.h>
10 #include <morello_core.h>
11 #include <morello_system_clock.h>
12
13 #include <mod_clock.h>
14 #include <mod_css_clock.h>
15 #include <mod_morello_pll.h>
16 #include <mod_pik_clock.h>
17 #include <mod_power_domain.h>
18
19 #include <fwk_element.h>
20 #include <fwk_module.h>
21 #include <fwk_module_idx.h>
22
23 static const struct fwk_element clock_dev_desc_table[CLOCK_IDX_COUNT + 1] = {
24 [CLOCK_IDX_INTERCONNECT] = {
25 .name = "Interconnect",
26 .data = &((struct mod_clock_dev_config) {
27 .driver_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_PIK_CLOCK,
28 CLOCK_PIK_IDX_INTERCONNECT),
29 .api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_PIK_CLOCK,
30 MOD_PIK_CLOCK_API_TYPE_CLOCK),
31 }),
32 },
33 [CLOCK_IDX_CPU_GROUP0] = {
34 .name = "CPU_GROUP0",
35 .data = &((struct mod_clock_dev_config) {
36 .driver_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CSS_CLOCK,
37 CLOCK_CSS_IDX_CPU_GROUP0),
38 .api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_CSS_CLOCK,
39 MOD_CSS_CLOCK_API_TYPE_CLOCK),
40 }),
41 },
42 [CLOCK_IDX_CPU_GROUP1] = {
43 .name = "CPU_GROUP1",
44 .data = &((struct mod_clock_dev_config) {
45 .driver_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CSS_CLOCK,
46 CLOCK_CSS_IDX_CPU_GROUP1),
47 .api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_CSS_CLOCK,
48 MOD_CSS_CLOCK_API_TYPE_CLOCK),
49 }),
50 },
51 [CLOCK_IDX_GPU] = {
52 .name = "GPU",
53 .data = &((struct mod_clock_dev_config) {
54 .driver_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CSS_CLOCK,
55 CLOCK_CSS_IDX_GPU),
56 .api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_CSS_CLOCK,
57 MOD_CSS_CLOCK_API_TYPE_CLOCK),
58 }),
59 },
60 [CLOCK_IDX_DPU] = {
61 .name = "DPU",
62 .data = &((struct mod_clock_dev_config) {
63 .driver_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_CSS_CLOCK,
64 CLOCK_CSS_IDX_DPU),
65 .api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_CSS_CLOCK,
66 MOD_CSS_CLOCK_API_TYPE_CLOCK),
67 }),
68 },
69 [CLOCK_IDX_PIXEL_0] = {
70 .name = "PIXEL_0",
71 .data = &((struct mod_clock_dev_config) {
72 .driver_id = FWK_ID_ELEMENT_INIT(FWK_MODULE_IDX_MORELLO_PLL,
73 CLOCK_PLL_IDX_PXL),
74 .api_id = FWK_ID_API_INIT(FWK_MODULE_IDX_MORELLO_PLL,
75 MOD_MORELLO_PLL_API_TYPE_DEFAULT),
76 }),
77 },
78 { 0 }, /* Termination description. */
79 };
80
clock_get_dev_desc_table(fwk_id_t module_id)81 static const struct fwk_element *clock_get_dev_desc_table(fwk_id_t module_id)
82 {
83 unsigned int i;
84 struct mod_clock_dev_config *dev_config;
85
86 for (i = 0; i < CLOCK_IDX_COUNT; i++) {
87 dev_config =
88 (struct mod_clock_dev_config *)clock_dev_desc_table[i].data;
89 dev_config->pd_source_id = fwk_id_build_element_id(
90 fwk_module_id_power_domain, PD_SINGLE_CHIP_IDX_SYSTOP0);
91 }
92
93 return clock_dev_desc_table;
94 }
95
96 const struct fwk_module_config config_clock = {
97 .elements = FWK_MODULE_DYNAMIC_ELEMENTS(clock_get_dev_desc_table),
98 .data = &((struct mod_clock_config){
99 .pd_transition_notification_id = FWK_ID_NOTIFICATION_INIT(
100 FWK_MODULE_IDX_POWER_DOMAIN,
101 MOD_PD_NOTIFICATION_IDX_POWER_STATE_TRANSITION),
102 .pd_pre_transition_notification_id = FWK_ID_NOTIFICATION_INIT(
103 FWK_MODULE_IDX_POWER_DOMAIN,
104 MOD_PD_NOTIFICATION_IDX_POWER_STATE_PRE_TRANSITION),
105 }),
106
107 };
108