1 /*
2  * Arm SCP/MCP Software
3  * Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved.
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 
8 #ifndef N1SDP_MCP_MMAP_H
9 #define N1SDP_MCP_MMAP_H
10 
11 #include <stdint.h>
12 
13 /*
14  * Top-level base addresses
15  */
16 #define MCP_SOC_EXPANSION1_BASE       UINT32_C(0x01000000)
17 #define MCP_SOC_EXPANSION2_BASE       UINT32_C(0x21000000)
18 #define MCP_SOC_EXPANSION3_BASE       UINT32_C(0x40000000)
19 #define MCP_SOC_EXPANSION4_BASE       UINT32_C(0x48000000)
20 #define MCP_PERIPH_BASE               UINT32_C(0x4C000000)
21 #define MCP_MEMORY_CONTROLLER         UINT32_C(0x4E000000)
22 #define MCP_POWER_PERIPH_BASE         UINT32_C(0x50000000)
23 #define MCP_SYS0_BASE                 UINT32_C(0x60000000)
24 #define MCP_SYS1_BASE                 UINT32_C(0xA0000000)
25 #define MCP_PPB_BASE_INTERNAL         UINT32_C(0xE0000000)
26 #define MCP_PPB_BASE_EXTERNAL         UINT32_C(0xE0040000)
27 
28 /*
29  * Peripherals
30  */
31 #define MCP_REFCLK_CNTCTL_BASE        (MCP_PERIPH_BASE)
32 #define MCP_REFCLK_CNTBASE0_BASE      (MCP_PERIPH_BASE + 0x1000)
33 #define MCP_UART0_BASE                (MCP_PERIPH_BASE + 0x2000)
34 #define MCP_WDOG_BASE                 (MCP_PERIPH_BASE + 0x6000)
35 
36 #define MCP_I2C0_BASE                 (0x3FFFE000)
37 #define MCP_I2C1_BASE                 (0x3FFFF000)
38 
39 /*
40  * Power control peripherals
41  */
42 #define MCP_PIK_BASE                  (MCP_POWER_PERIPH_BASE)
43 
44 /*
45  * Base addresses of MHUv1 devices
46  */
47 #define MCP_MHU_AP_BASE               (MCP_PERIPH_BASE + 0x400000)
48 #define MCP_MHU_SCP_BASE              UINT32_C(0x45600000)
49 
50 #define MHU_MCP_TO_AP_NS              (MCP_MHU_AP_BASE + 0x0020)
51 #define MHU_AP_TO_MCP_NS              (MCP_MHU_AP_BASE + 0x0120)
52 #define MHU_MCP_TO_AP_S               (MCP_MHU_AP_BASE + 0x0200)
53 #define MHU_AP_TO_MCP_S               (MCP_MHU_AP_BASE + 0x0300)
54 
55 #define MHU_SCP_TO_MCP_NS             (MCP_MHU_SCP_BASE + 0x0020)
56 #define MHU_MCP_TO_SCP_NS             (MCP_MHU_SCP_BASE + 0x0120)
57 #define MHU_SCP_TO_MCP_S              (MCP_MHU_SCP_BASE + 0x0200)
58 #define MHU_MCP_TO_SCP_S              (MCP_MHU_SCP_BASE + 0x0300)
59 
60 /*
61  * Shared memory regions
62  */
63 #define MCP_AP_SHARED_SECURE_RAM      (MCP_PERIPH_BASE + 0x420000)
64 #define MCP_AP_SHARED_NONSECURE_RAM   (MCP_PERIPH_BASE + 0x410000)
65 #define MCP_SCP_SHARED_SECURE_RAM     (0x45620000)
66 #define MCP_SCP_SHARED_NONSECURE_RAM  (0x45610000)
67 
68 #endif /* N1SDP_MCP_MMAP_H */
69