1 /*
2 * Arm SCP/MCP Software
3 * Copyright (c) 2022, Linaro Limited and Contributors. All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #include <fwk_module.h>
9 #include <mod_system_pll.h>
10
11 uint32_t ctrl_reg[7];
12
13 static const struct fwk_element system_pll_element_table[] = {
14 {
15 .name = "CPU_PLL_0",
16 .data = &((struct mod_system_pll_dev_config) {
17 .control_reg = &ctrl_reg[0],
18 .initial_rate = 1330 * FWK_MHZ,
19 .min_rate = MOD_SYSTEM_PLL_MIN_RATE,
20 .max_rate = MOD_SYSTEM_PLL_MAX_RATE,
21 .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL,
22 .defer_initialization = false,
23 }),
24 },
25 {
26 .name = "CPU_PLL_1",
27 .data = &((struct mod_system_pll_dev_config) {
28 .control_reg = &ctrl_reg[1],
29 .initial_rate = 1750 * FWK_MHZ,
30 .min_rate = MOD_SYSTEM_PLL_MIN_RATE,
31 .max_rate = MOD_SYSTEM_PLL_MAX_RATE,
32 .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL,
33 .defer_initialization = false,
34 }),
35 },
36 {
37 .name = "GPU_PLL",
38 .data = &((struct mod_system_pll_dev_config) {
39 .control_reg = &ctrl_reg[2],
40 .initial_rate = 600 * FWK_MHZ,
41 .min_rate = MOD_SYSTEM_PLL_MIN_RATE,
42 .max_rate = MOD_SYSTEM_PLL_MAX_RATE,
43 .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL,
44 .defer_initialization = false,
45 }),
46 },
47 {
48 .name = "DPU_PLL",
49 .data = &((struct mod_system_pll_dev_config) {
50 .control_reg = &ctrl_reg[3],
51 .initial_rate = 260 * FWK_MHZ,
52 .min_rate = MOD_SYSTEM_PLL_MIN_RATE,
53 .max_rate = MOD_SYSTEM_PLL_MAX_RATE,
54 .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL,
55 .defer_initialization = false,
56 }),
57 },
58 {
59 .name = "VPU_PLL",
60 .data = &((struct mod_system_pll_dev_config) {
61 .control_reg = &ctrl_reg[4],
62 .initial_rate = 600 * FWK_MHZ,
63 .min_rate = MOD_SYSTEM_PLL_MIN_RATE,
64 .max_rate = MOD_SYSTEM_PLL_MAX_RATE,
65 .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL,
66 .defer_initialization = false,
67 }),
68 },
69 {
70 .name = "PIX0_PLL",
71 .data = &((struct mod_system_pll_dev_config) {
72 .control_reg = &ctrl_reg[5],
73 .initial_rate = 594 * FWK_MHZ,
74 .min_rate = 12500 * FWK_KHZ,
75 .max_rate = 594 * FWK_MHZ,
76 .min_step = 250 * FWK_KHZ,
77 .defer_initialization = false,
78 }),
79 },
80 {
81 .name = "PIX1_PLL",
82 .data = &((struct mod_system_pll_dev_config) {
83 .control_reg = &ctrl_reg[6],
84 .initial_rate = 594 * FWK_MHZ,
85 .min_rate = 12500 * FWK_KHZ,
86 .max_rate = 594 * FWK_MHZ,
87 .min_step = 250 * FWK_KHZ,
88 .defer_initialization = false,
89 }),
90 },
91 { 0 }, /* Termination description. */
92 };
93
system_pll_get_element_table(fwk_id_t module_id)94 static const struct fwk_element *system_pll_get_element_table
95 (fwk_id_t module_id)
96 {
97 return system_pll_element_table;
98 }
99
100 struct fwk_module_config config_system_pll = {
101 .elements = FWK_MODULE_DYNAMIC_ELEMENTS(system_pll_get_element_table),
102 };
103