1 /*
2  * Renesas SCP/MCP Software
3  * Copyright (c) 2020-2021, Renesas Electronics Corporation. All rights
4  * reserved.
5  *
6  * SPDX-License-Identifier: BSD-3-Clause
7  */
8 
9 #ifndef SCIF_H
10 #define SCIF_H
11 
12 #include <rcar_mmap.h>
13 
14 #include <fwk_macros.h>
15 
16 #define SCIF_INTERNAL_CLK 0 /* Internal clock(S3D4:66.66MHz) */
17 #define SCIF_EXTARNAL_CLK 1 /* External clock(SCK2:14.7456MHz) */
18 #define SCIF_CLK SCIF_INTERNAL_CLK
19 
20 struct scif_reg {
21     FWK_RW uint16_t SCSMR; /* H'00 */
22     uint16_t RESERVED1; /* H'02 */
23     FWK_RW uint8_t SCBRR; /* H'04 */
24     uint8_t RESERVED2; /* H'05 */
25     uint16_t RESERVED3; /* H'06 */
26     FWK_RW uint16_t SCSCR; /* H'08 */
27     uint16_t RESERVED4; /* H'0A */
28     FWK_W uint8_t SCFTDR; /* H'0C */
29     uint8_t RESERVED5; /* H'0D */
30     uint16_t RESERVED6; /* H'0E */
31     FWK_RW uint16_t SCFSR; /* H'10 */
32     uint16_t RESERVED7; /* H'12 */
33     FWK_R uint8_t SCFRDR; /* H'14 */
34     uint8_t RESERVED8; /* H'15 */
35     uint16_t RESERVED9; /* H'16 */
36     FWK_RW uint16_t SCFCR; /* H'18 */
37     uint16_t RESERVED10; /* H'1A */
38     FWK_R uint16_t SCFDR; /* H'1C */
39     uint16_t RESERVED11; /* H'1E */
40     FWK_RW uint16_t SCSPTR; /* H'20 */
41     uint16_t RESERVED12; /* H'22 */
42     FWK_RW uint16_t SCLSR; /* H'24 */
43     uint16_t RESERVED13; /* H'26 */
44     uint32_t RESERVED14; /* H'28 */
45     uint32_t RESERVED15; /* H'2C */
46     FWK_RW uint16_t DL; /* H'30 */
47     uint16_t RESERVED16; /* H'32 */
48     FWK_RW uint16_t CKS; /* H'34 */
49 };
50 
51 #define CPG_SMSTPCR2 (CPG_BASE + 0x0138)
52 #define CPG_SMSTPCR3 (CPG_BASE + 0x013C)
53 #define CPG_MSTPSR2 (CPG_BASE + 0x0040)
54 #define CPG_MSTPSR3 (CPG_BASE + 0x0048)
55 #define CPG_CPGWPR (CPG_BASE + 0x0900)
56 
57 #define PRR (0xFFF00044)
58 #define PRR_PRODUCT_MASK (0x00007F00)
59 #define PRR_CUT_MASK (0x000000FF)
60 #define PRR_PRODUCT_H3_VER_10 (0x00004F00) /* R-Car H3 Ver.1.0 */
61 
62 #define SCSMR_CA_MASK (1 << 7)
63 #define SCSMR_CA_ASYNC (0x0000)
64 #define SCSMR_CHR_MASK (1 << 6)
65 #define SCSMR_CHR_8 (0x0000)
66 #define SCSMR_PE_MASK (1 << 5)
67 #define SCSMR_PE_DIS (0x0000)
68 #define SCSMR_STOP_MASK (1 << 3)
69 #define SCSMR_STOP_1 (0x0000)
70 #define SCSMR_CKS_MASK (3 << 0)
71 #define SCSMR_CKS_DIV1 (0x0000)
72 #define SCSMR_INIT_DATA \
73     (SCSMR_CA_ASYNC + SCSMR_CHR_8 + SCSMR_PE_DIS + SCSMR_STOP_1 + \
74      SCSMR_CKS_DIV1)
75 
76 #define MSTP310 (1 << 10)
77 #define MSTP26 (1 << 6)
78 
79 #define SCSCR_TE_MASK (1 << 5)
80 #define SCSCR_TE_DIS (0x0000)
81 #define SCSCR_TE_EN (0x0020)
82 #define SCSCR_RE_MASK (1 << 4)
83 #define SCSCR_RE_DIS (0x0000)
84 #define SCSCR_RE_EN (0x0010)
85 #define SCSCR_CKE_MASK (3 << 0)
86 #define SCSCR_CKE_INT (0x0000)
87 #define SCSCR_CKE_BRG (0x0002)
88 #if SCIF_CLK == SCIF_EXTARNAL_CLK
89 #    define SCSCR_CKE_INT_CLK (SCSCR_CKE_BRG)
90 #else
91 #    define SCSCR_CKE_INT_CLK (SCSCR_CKE_INT)
92 #endif
93 
94 #define SCFSR_INIT_DATA (0x0000)
95 
96 #define SCFCR_TFRST_EN (0x0004)
97 #define SCFCR_RFRS_EN (0x0002)
98 
99 #define FIFO_SIZE_BIT (5)
100 #define FIFO_MASK ((1 << FIFO_SIZE_BIT) - 1)
101 #define FIFO_R_SHIFT (0)
102 #define FIFO_T_SHIFT (8)
103 #define FIFO_FULL (16)
104 #define GET_SCFDR_T(reg) ((reg->SCFDR >> FIFO_T_SHIFT) & FIFO_MASK)
105 
106 #define SCFCR_TTRG_8 (0x0000)
107 #define SCFCR_INIT_DATA (SCFCR_TTRG_8)
108 
109 #define SCBRR_115200BPS (17) /* 115200bps@66MHz */
110 #define SCBRR_230400BPS (8) /* 230400bps@66MHz */
111 
112 #endif /* SCIF_H */
113