1 /*
2  * Arm SCP/MCP Software
3  * Copyright (c) 2022, Arm Limited and Contributors. All rights reserved.
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 
8 #include "lcp_mmap.h"
9 #include "mod_armv8m_mpu.h"
10 
11 #include <fwk_macros.h>
12 #include <fwk_module.h>
13 
14 #include <fmw_cmsis.h>
15 
16 static const uint8_t attributes[] = {
17     /* Device memory, non Gathering, non Re-ordering, non Early Write
18        Acknowledgement */
19     [MPU_ATTR_0] =
20         ARM_MPU_ATTR(ARM_MPU_ATTR_DEVICE, ARM_MPU_ATTR_DEVICE_nGnRnE),
21     /* Normal memory, non Cacheable */
22     [MPU_ATTR_1] =
23         ARM_MPU_ATTR(ARM_MPU_ATTR_NON_CACHEABLE, ARM_MPU_ATTR_NON_CACHEABLE),
24 };
25 
26 static const ARM_MPU_Region_t regions[] = {
27     {
28         /* LCP_CORE_TCM_REGION*/
29         .RBAR = ARM_MPU_RBAR(
30             LCP_CORE_ITCM_REGION_START, /* BASE */
31             ARM_MPU_SH_NON, /* SH */
32             0, /* RO */
33             0, /* NP */
34             0 /* XN */),
35         .RLAR = ARM_MPU_RLAR(LCP_CORE_ITCM_REGION_END, MPU_ATTR_1),
36     },
37     {
38         /* LCP_CORE_DTCM_REGION*/
39         .RBAR = ARM_MPU_RBAR(
40             LCP_CORE_DTCM_REGION_START, /* BASE */
41             ARM_MPU_SH_INNER, /* SH */
42             0, /* RO */
43             0, /* NP */
44             1 /* XN */),
45         .RLAR = ARM_MPU_RLAR(LCP_CORE_DTCM_REGION_END, MPU_ATTR_1),
46     },
47     {
48         /* LCP_CORE_PERIPERAL_REGION */
49         .RBAR = ARM_MPU_RBAR(
50             LCP_CORE_PERIPHERAL_REGION_START, /* BASE */
51             ARM_MPU_SH_NON, /* SH */
52             0, /* RO */
53             0, /* NP */
54             1 /* XN */),
55         .RLAR = ARM_MPU_RLAR(LCP_CORE_PERIPHERAL_REGION_END, MPU_ATTR_0),
56     },
57     {
58         /* LCP_SRAM_REGION*/
59         .RBAR = ARM_MPU_RBAR(
60             LCP_SRAM_REGION_START, /* BASE */
61             ARM_MPU_SH_OUTER, /* SH */
62             0, /* RO */
63             0, /* NP */
64             1 /* XN */),
65         .RLAR = ARM_MPU_RLAR(LCP_SRAM_REGION_END, MPU_ATTR_1),
66     },
67     {
68         /* LCP_DEVICE_REGION */
69         .RBAR = ARM_MPU_RBAR(
70             LCP_DEVICE_REGION_START, /* BASE */
71             ARM_MPU_SH_OUTER, /* SH */
72             0, /* RO */
73             0, /* NP */
74             1 /* XN */),
75         .RLAR = ARM_MPU_RLAR(LCP_DEVICE_REGION_END, MPU_ATTR_0),
76     },
77 };
78 
79 const struct fwk_module_config config_armv8m_mpu = {
80     .data = &((struct mod_armv8m_mpu_config){
81         .region_count = FWK_ARRAY_SIZE(regions),
82         .regions = regions,
83         .attributes_count = FWK_ARRAY_SIZE(attributes),
84         .attributes = attributes,
85     }),
86 };
87