1 /* 2 * Arm SCP/MCP Software 3 * Copyright (c) 2017-2022, Arm Limited and Contributors. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef FMW_CMSIS_SCP_H 9 #define FMW_CMSIS_SCP_H 10 11 #include <stdint.h> 12 13 #define __CHECK_DEVICE_DEFINES 14 #define __CM7_REV 0x0000U 15 #define __FPU_PRESENT 0U 16 #define __MPU_PRESENT 1U 17 #define __ICACHE_PRESENT 0U 18 #define __DCACHE_PRESENT 0U 19 #define __DTCM_PRESENT 0U 20 #define __NVIC_PRIO_BITS 3U 21 #define __Vendor_SysTickConfig 0U 22 #define __VTOR_PRESENT 1U 23 24 extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock)*/ 25 26 typedef enum IRQn { 27 Reset_IRQn = -15, 28 NonMaskableInt_IRQn = -14, 29 HardFault_IRQn = -13, 30 MemoryManagement_IRQn = -12, 31 BusFault_IRQn = -11, 32 UsageFault_IRQn = -10, 33 SVCall_IRQn = -5, 34 DebugMonitor_IRQn = -4, 35 PendSV_IRQn = -2, 36 SysTick_IRQn = -1, 37 38 RESERVED0_IRQ = 0, /* Reserved */ 39 CDBG_PWR_UP_REQ_IRQ = 1, /* Coresight Debug Power Request */ 40 CSYS_PWR_UP_REQ_IRQ = 2, /* Coresight System Power Request */ 41 CDBG_RST_REQ_IRQ = 3, /* Coresight Debug Reset Request */ 42 GIC_EXT_WAKEUP_IRQ = 4, /* External GIC Wakeup Request */ 43 RESERVED5_IRQ = 5, /* Reserved */ 44 RESERVED6_IRQ = 6, /* Reserved */ 45 RESERVED7_IRQ = 7, /* Reserved */ 46 RESERVED8_IRQ = 8, /* Reserved */ 47 RESERVED9_IRQ = 9, /* Reserved */ 48 RESERVED10_IRQ = 10, /* Reserved */ 49 RESERVED11_IRQ = 11, /* Reserved */ 50 RESERVED12_IRQ = 12, /* Reserved */ 51 RESERVED13_IRQ = 13, /* Reserved */ 52 RESERVED14_IRQ = 14, /* Reserved */ 53 RESERVED15_IRQ = 15, /* Reserved */ 54 SOC_WAKEUP0_IRQ = 16, /* SoC Expansion Wakeup */ 55 SOC_WAKEUP1_IRQ = 17, /* SoC Expansion Wakeup */ 56 SOC_WAKEUP2_IRQ = 18, /* SoC Expansion Wakeup */ 57 SOC_WAKEUP3_IRQ = 19, /* SoC Expansion Wakeup */ 58 SOC_WAKEUP4_IRQ = 20, /* SoC Expansion Wakeup */ 59 SOC_WAKEUP5_IRQ = 21, /* SoC Expansion Wakeup */ 60 SOC_WAKEUP6_IRQ = 22, /* SoC Expansion Wakeup */ 61 SOC_WAKEUP7_IRQ = 23, /* SoC Expansion Wakeup */ 62 SOC_WAKEUP8_IRQ = 24, /* SoC Expansion Wakeup */ 63 SOC_WAKEUP9_IRQ = 25, /* SoC Expansion Wakeup */ 64 SOC_WAKEUP10_IRQ = 26, /* SoC Expansion Wakeup */ 65 SOC_WAKEUP11_IRQ = 27, /* SoC Expansion Wakeup */ 66 SOC_WAKEUP12_IRQ = 28, /* SoC Expansion Wakeup */ 67 SOC_WAKEUP13_IRQ = 29, /* SoC Expansion Wakeup */ 68 SOC_WAKEUP14_IRQ = 30, /* SoC Expansion Wakeup */ 69 SOC_WAKEUP15_IRQ = 31, /* SoC Expansion Wakeup */ 70 RESERVED32_IRQ = 32, /* Reserved */ 71 TIMREFCLK_IRQ = 33, /* REFCLK Physical Timer */ 72 SYS_GEN_TIMER_SYNC_IRQ = 34, /* System Generic Timer synchronization */ 73 CSTS_SYNC_IRQ = 35, /* Coresight Time stamp synchronization */ 74 RESERVED36_IRQ = 36, /* Reserved */ 75 CTI_TRIGGER0_IRQ = 37, /* SCP CTI Trigger */ 76 CTI_TRIGGER1_IRQ = 38, /* SCP CTI Trigger */ 77 GIC_ERROR_ECC_IRQ = 39, /* GIC Error (ECC Fatal) */ 78 GIC_ERROR_AXIM_IRQ = 40, /* GIC Error (AXIM) */ 79 RESERVED41_IRQ = 41, /* Reserved */ 80 AON_UART_IRQ = 42, /* Always on UART */ 81 RESERVED43_IRQ = 43, /* Reserved */ 82 GEN_WD_WS0_IRQ = 44, /* Generic Watchdog timer WS0 */ 83 GEN_WD_WS1_IRQ = 45, /* Generic Watchdog timer WS1 */ 84 TRUSTED_WD_WS0_IRQ = 46, /* Trusted Watchdog timer WS0 */ 85 TRUSTED_WD_WS1_IRQ = 47, /* Trusted Watchdog timer WS1 */ 86 APPS_UART_IRQ = 48, /* Application UART */ 87 RESERVED49_IRQ = 49, /* Reserved */ 88 PPU_CORES0_IRQ = 89 50, /* Consolidated PPU Interrupt for cores 1-32, 129-160 */ 90 PPU_CORES1_IRQ = 91 51, /* Consolidated PPU Interrupt for cores 33-64, 161-192 */ 92 PPU_CORES2_IRQ = 93 52, /* Consolidated PPU Interrupt for cores 65-96, 193-224 */ 94 PPU_CORES3_IRQ = 95 53, /* Consolidated PPU Interrupt for cores 97-128, 225-256 */ 96 PPU_CLUSTERS_IRQ = 54, /* Consolidated clusters PPU */ 97 PLL_CORES0_LOCK_IRQ = 98 55, /* Consolidated PLL lock for PLLs 1-32, 65-96, 129-160, 193-224 */ 99 PLL_CORES1_LOCK_IRQ = 100 56, /* Consolidated PLL lock for PLLs 33-64, 97-128, 161-192, 225-256 */ 101 PLL_CORES0_UNLOCK_IRQ = 102 57, /* Consolidated PLL unlock for PLLs 1-32, 65-96, 129-160, 193-224 */ 103 PLL_CORES1_UNLOCK_IRQ = 58, /* Consolidated PLL unlock for PLLs 33-64, 104 97-128, 161-192, 225-256 */ 105 FAULT_CORES0_IRQ = 59, /* Consolidated fault IRQ for cores 1-32, 129-160 */ 106 FAULT_CORES1_IRQ = 60, /* Consolidated fault IRQ for cores 33-64, 161-192 */ 107 FAULT_CORES2_IRQ = 61, /* Consolidated fault IRQ for cores 65-96, 193-224 */ 108 FAULT_CORES3_IRQ = 109 62, /* Consolidated fault IRQ for cores 97-128, 225-256 */ 110 FAULT_CLUSTERS_IRQ = 63, /* Consolidated clusters fault */ 111 ECC_CORES0_ERROR_IRQ = 112 64, /* Consolidated ECC ERROR for cores 1-32, 129-160 */ 113 ECC_CORES1_ERROR_IRQ = 114 65, /* Consolidated ECC ERROR for cores 33-64, 161-192 */ 115 ECC_CORES2_ERROR_IRQ = 116 66, /* Consolidated ECC ERROR for cores 65-96, 193-224 */ 117 ECC_CORES3_ERROR_IRQ = 118 67, /* Consolidated ECC ERROR for cores 96-128, 225-256 */ 119 ECC_CLUSTERS_ERROR_IRQ = 68, /* Consolidated clusters ECC ERROR */ 120 PLL_CLUSTERS_LOCK_IRQ = 69, /* Consolidated clusters PLL Lock */ 121 PLL_CLUSTERS_UNLOCK_IRQ = 70, /* Consolidated clusters PLL Unlock*/ 122 RESERVED71_IRQ = 71, /* Reserved */ 123 RESERVED72_IRQ = 72, /* Reserved */ 124 RESERVED73_IRQ = 73, /* Reserved */ 125 RESERVED74_IRQ = 74, /* Reserved */ 126 RESERVED75_IRQ = 75, /* Reserved */ 127 RESERVED76_IRQ = 76, /* Reserved */ 128 RESERVED77_IRQ = 77, /* Reserved */ 129 RESERVED78_IRQ = 78, /* Reserved */ 130 RESERVED79_IRQ = 79, /* Reserved */ 131 RESERVED80_IRQ = 80, /* Reserved */ 132 RESERVED81_IRQ = 81, /* Reserved */ 133 MHU_AP_NONSEC_IRQ = 82, /* MHU non-secure irq bewteen SCP and AP */ 134 MHU_AP_SEC_IRQ = 83, /* MHU secure irq bewteen SCP and AP */ 135 MHU_MCP_NONSEC_IRQ = 84, /* MHU non-secure irq between SCP and MCP */ 136 MHU_MCP_SEC_IRQ = 85, /* MHU secure irq bewteen SCP and MCP */ 137 RESERVED86_IRQ = 86, /* Reserved */ 138 RESERVED87_IRQ = 87, /* Reserved */ 139 RESERVED88_IRQ = 88, /* Reserved */ 140 RESERVED89_IRQ = 89, /* Reserved */ 141 TIMER_CLUSTERS_IRQ = 90, /* Consolidated clusters timer interrupt */ 142 RESERVED91_IRQ = 91, /* Reserved */ 143 RESERVED92_IRQ = 92, /* Reserved */ 144 RESERVED93_IRQ = 93, /* Reserved */ 145 MMU_TCU_RASIRPT_IRQ = 94, /* Consolidated MMU RAS */ 146 MMU_TBU_RASIRPT_IRQ = 95, /* Consolidated TBU RAS */ 147 INT_PPU_IRQ = 96, /* PPU interrupt from Interconnect PPU */ 148 INT_ERRNS_IRQ = 97, /* Non-Sec error interrupt from Interconnect PPU */ 149 INT_ERRS_IRQ = 98, /* Secure error interrupt from Interconnect PPU */ 150 INT_FAULTS_IRQ = 99, /* Secure fault interrupt from Interconnect PPU */ 151 INT_FAULTNS_IRQ = 100, /* Non-Sec fault interrupt from Interconnect PPU */ 152 INT_PMU_IRQ = 101, /* PMU count overflow interrupt */ 153 RESERVED102_IRQ = 102, /* Reserved */ 154 RESERVED103_IRQ = 103, /* Reserved */ 155 RESERVED104_IRQ = 104, /* Reserved */ 156 RESERVED105_IRQ = 105, /* Reserved */ 157 RESERVED106_IRQ = 106, /* Reserved */ 158 RESERVED107_IRQ = 107, /* Reserved */ 159 RESERVED108_IRQ = 108, /* Reserved */ 160 RESERVED109_IRQ = 109, /* Reserved */ 161 RESERVED110_IRQ = 110, /* Reserved */ 162 RESERVED111_IRQ = 111, /* Reserved */ 163 RESERVED112_IRQ = 112, /* Reserved */ 164 RESERVED113_IRQ = 113, /* Reserved */ 165 RESERVED114_IRQ = 114, /* Reserved */ 166 RESERVED115_IRQ = 115, /* Reserved */ 167 RESERVED116_IRQ = 116, /* Reserved */ 168 RESERVED117_IRQ = 117, /* Reserved */ 169 RESERVED118_IRQ = 118, /* Reserved */ 170 RESERVED119_IRQ = 119, /* Reserved */ 171 PPU_DBGCH0_IRQ = 120, /* Debug Chain 0 PPU */ 172 PPU_DBGCH1_IRQ = 121, /* Debug Chain 1 PPU */ 173 PPU_DBGCH2_IRQ = 122, /* Debug Chain 2 PPU */ 174 PPU_DBGCH3_IRQ = 123, /* Debug Chain 3 PPU */ 175 PPU_DBGCH4_IRQ = 124, /* Debug Chain 4 PPU */ 176 PPU_DBGCH5_IRQ = 125, /* Debug Chain 5 PPU */ 177 PPU_DBGCH6_IRQ = 126, /* Debug Chain 6 PPU */ 178 PPU_DBGCH7_IRQ = 127, /* Debug Chain 7 PPU */ 179 RESERVED128_IRQ = 128, /* Reserved */ 180 RESERVED129_IRQ = 129, /* Reserved */ 181 DEBUG_PIK_IRQ = 130, /* DEBUG PIK */ 182 PPU_LOGIC_IRQ = 131, /* PPU LOGIC */ 183 RESERVED132_IRQ = 132, /* Reserved */ 184 RESERVED133_IRQ = 133, /* Reserved */ 185 RESERVED134_IRQ = 134, /* Reserved */ 186 PPU_SRAM_IRQ = 135, /* PPU SRAM */ 187 RESERVED136_IRQ = 136, /* Reserved */ 188 RESERVED137_IRQ = 137, /* Reserved */ 189 RESERVED138_IRQ = 138, /* Reserved */ 190 MCP_WD_WS1_IRQ = 139, /* MCP watchdog reset */ 191 PLL_SYS_LOCK_IRQ = 140, /* System PLL Lock */ 192 PLL_SYS_UNLOCK_IRQ = 141, /* System PLL Unlock */ 193 PLL_INT_LOCK_IRQ = 142, /* Interconnect PLL Lock */ 194 PLL_INT_UNLOCK_IRQ = 143, /* Interconnect PLL Unlock */ 195 RESERVED144_IRQ = 144, /* Reserved */ 196 RESERVED145_IRQ = 145, /* Reserved */ 197 RESERVED146_IRQ = 146, /* Reserved */ 198 RESERVED147_IRQ = 147, /* Reserved */ 199 RESERVED148_IRQ = 148, /* Reserved */ 200 RESERVED149_IRQ = 149, /* Reserved */ 201 RESERVED150_IRQ = 150, /* Reserved */ 202 RESERVED151_IRQ = 151, /* Reserved */ 203 RESERVED152_IRQ = 152, /* Reserved */ 204 RESERVED153_IRQ = 153, /* Reserved */ 205 RESERVED154_IRQ = 154, /* Reserved */ 206 RESERVED155_IRQ = 155, /* Reserved */ 207 RESERVED156_IRQ = 156, /* Reserved */ 208 RESERVED157_IRQ = 157, /* Reserved */ 209 RESERVED158_IRQ = 158, /* Reserved */ 210 RESERVED159_IRQ = 159, /* Reserved */ 211 RESERVED160_IRQ = 160, /* Reserved */ 212 RESERVED161_IRQ = 161, /* Reserved */ 213 RESERVED162_IRQ = 162, /* Reserved */ 214 RESERVED163_IRQ = 163, /* Reserved */ 215 RESERVED164_IRQ = 164, /* Reserved */ 216 RESERVED165_IRQ = 165, /* Reserved */ 217 RESERVED166_IRQ = 166, /* Reserved */ 218 RESERVED167_IRQ = 167, /* Reserved */ 219 RESERVED168_IRQ = 168, /* Reserved */ 220 RESERVED169_IRQ = 169, /* Reserved */ 221 RESERVED170_IRQ = 170, /* Reserved */ 222 RESERVED171_IRQ = 171, /* Reserved */ 223 RESERVED172_IRQ = 172, /* Reserved */ 224 RESERVED173_IRQ = 173, /* Reserved */ 225 PLL_DMC_LOCK_IRQ = 174, /* DMC PLL LOCK */ 226 PLL_DMC_UNLOCK_IRQ = 175, /* DMC PLL LOCK */ 227 RESERVED176_IRQ = 176, /* Reserved */ 228 RESERVED177_IRQ = 177, /* Reserved */ 229 RESERVED178_IRQ = 178, /* Reserved */ 230 RESERVED179_IRQ = 179, /* Reserved */ 231 DMCS0_MISC_OFLOW_IRQ = 180, /* DMC 0/4 Combined Error Overflow */ 232 DMCS0_ERR_OFLOW_IRQ = 181, /* DMC 0/4 Error Overflow */ 233 DMCS0_ECC_ERR_INT_IRQ = 182, /* DMC 0/4 ECC Error Int */ 234 DMCS0_MISC_ACCESS_INT_IRQ = 235 183, /* DMC 0/4 Combined Miscellaneous access int */ 236 DMCS0_TEMPERATURE_EVENT_INT_IRQ = 184, /* DMC 0/4 Temperature event int */ 237 DMCS0_FAILED_ACCESS_INT_IRQ = 185, /* DMC 0/4 Failed access int */ 238 DMCS0_MGR_INT_IRQ = 186, /* DMC 0/4 combined manager int */ 239 DMCS1_MISC_OFLOW_IRQ = 187, /* DMC 1/5 Combined Error Overflow */ 240 DMCS1_ERR_OFLOW_IRQ = 188, /* DMC 1/5 Error Overflow */ 241 DMCS1_ECC_ERR_INT_IRQ = 189, /* DMC 1/5 ECC Error Int */ 242 DMCS1_MISC_ACCESS_INT_IRQ = 243 190, /* DMC 1/5 Combined Miscellaneous access int */ 244 DMCS1_TEMPERATURE_EVENT_INT_IRQ = 191, /* DMC 1/5 Temperature event int */ 245 DMCS1_FAILED_ACCESS_INT_IRQ = 192, /* DMC 1/5 Failed access int */ 246 DMCS1_MGR_INT_IRQ = 193, /* DMC 1/5 combined manager int */ 247 DMCS2_MISC_OFLOW_IRQ = 194, /* DMC 2/6 Combined Error Overflow */ 248 DMCS2_ERR_OFLOW_IRQ = 195, /* DMC 2/6 Error Overflow */ 249 DMCS2_ECC_ERR_INT_IRQ = 196, /* DMC 2/6 ECC Error Int */ 250 DMCS2_MISC_ACCESS_INT_IRQ = 251 197, /* DMC 2/6 Combined Miscellaneous access int */ 252 DMCS2_TEMPERATURE_EVENT_INT_IRQ = 198, /* DMC 2/6 Temperature event int */ 253 DMCS2_FAILED_ACCESS_INT_IRQ = 199, /* DMC 2/6 Failed access int */ 254 DMCS2_MGR_INT_IRQ = 200, /* DMC 2/6 combined manager int */ 255 DMCS3_MISC_OFLOW_IRQ = 201, /* DMC 3/7 Combined Error Overflow */ 256 DMCS3_ERR_OFLOW_IRQ = 202, /* DMC 3/7 Error Overflow */ 257 DMCS3_ECC_ERR_INT_IRQ = 203, /* DMC 3/7 ECC Error Int */ 258 DMCS3_MISC_ACCESS_INT_IRQ = 259 204, /* DMC 3/7 Combined Miscellaneous access int */ 260 DMCS3_TEMPERATURE_EVENT_INT_IRQ = 205, /* DMC 3/7 Temperature event int */ 261 DMCS3_FAILED_ACCESS_INT_IRQ = 206, /* DMC 3/7 Failed access int */ 262 DMCS3_MGR_INT_IRQ = 207, /* DMC 3/7 combined manager int */ 263 SCP_EXT_INTR0_IRQ = 208, /* SCP Customer Extension */ 264 SCP_EXT_INTR1_IRQ = 209, /* SCP Customer Extension */ 265 SCP_EXT_INTR2_IRQ = 210, /* SCP Customer Extension */ 266 SCP_EXT_INTR3_IRQ = 211, /* SCP Customer Extension */ 267 SCP_EXT_INTR4_IRQ = 212, /* SCP Customer Extension */ 268 SCP_EXT_INTR5_IRQ = 213, /* SCP Customer Extension */ 269 SCP_EXT_INTR6_IRQ = 214, /* SCP Customer Extension */ 270 SCP_EXT_INTR7_IRQ = 215, /* SCP Customer Extension */ 271 SCP_EXT_INTR8_IRQ = 216, /* SCP Customer Extension */ 272 SCP_EXT_INTR9_IRQ = 217, /* SCP Customer Extension */ 273 SCP_EXT_INTR10_IRQ = 218, /* SCP Customer Extension */ 274 SCP_EXT_INTR11_IRQ = 219, /* SCP Customer Extension */ 275 SCP_EXT_INTR12_IRQ = 220, /* SCP Customer Extension */ 276 SCP_EXT_INTR13_IRQ = 221, /* SCP Customer Extension */ 277 SCP_EXT_INTR14_IRQ = 222, /* SCP Customer Extension */ 278 SCP_EXT_INTR15_IRQ = 223, /* SCP Customer Extension */ 279 SCP_EXT_INTR16_IRQ = 224, /* SCP Customer Extension */ 280 SCP_EXT_INTR17_IRQ = 225, /* SCP Customer Extension */ 281 SCP_EXT_INTR18_IRQ = 226, /* SCP Customer Extension */ 282 SCP_EXT_INTR19_IRQ = 227, /* SCP Customer Extension */ 283 SCP_EXT_INTR20_IRQ = 228, /* SCP Customer Extension */ 284 SCP_EXT_INTR21_IRQ = 229, /* SCP Customer Extension */ 285 SCP_EXT_INTR22_IRQ = 230, /* SCP Customer Extension */ 286 SCP_EXT_INTR23_IRQ = 231, /* SCP Customer Extension */ 287 SCP_EXT_INTR24_IRQ = 232, /* SCP Customer Extension */ 288 SCP_EXT_INTR25_IRQ = 233, /* SCP Customer Extension */ 289 SCP_EXT_INTR26_IRQ = 234, /* SCP Customer Extension */ 290 SCP_EXT_INTR27_IRQ = 235, /* SCP Customer Extension */ 291 SCP_EXT_INTR28_IRQ = 236, /* SCP Customer Extension */ 292 SCP_EXT_INTR29_IRQ = 237, /* SCP Customer Extension */ 293 SCP_EXT_INTR30_IRQ = 238, /* SCP Customer Extension */ 294 SCP_EXT_INTR31_IRQ = 239, /* SCP Customer Extension */ 295 296 IRQn_MAX = INT16_MAX, 297 } IRQn_Type; 298 299 #include <core_cm7.h> 300 301 #endif /* FMW_CMSIS_SCP_H */ 302