1 /* 2 * Arm SCP/MCP Software 3 * Copyright (c) 2017-2022, Arm Limited and Contributors. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef MCP_RDN1E1_MMAP_H 9 #define MCP_RDN1E1_MMAP_H 10 11 #include <stdint.h> 12 13 /* 14 * Top-level base addresses 15 */ 16 #define MCP_SOC_EXPANSION1_BASE UINT32_C(0x01000000) 17 #define MCP_SOC_EXPANSION2_BASE UINT32_C(0x21000000) 18 #define MCP_SOC_EXPANSION3_BASE UINT32_C(0x40000000) 19 #define MCP_MHU_SCP_BASE UINT32_C(0x45600000) 20 #define MCP_SOC_EXPANSION4_BASE UINT32_C(0x48000000) 21 #define MCP_PERIPH_BASE UINT32_C(0x4C000000) 22 #define MCP_MEMORY_CONTROLLER UINT32_C(0x4E000000) 23 #define MCP_POWER_PERIPH_BASE UINT32_C(0x50000000) 24 #define MCP_SYS0_BASE UINT32_C(0x60000000) 25 #define MCP_SYS1_BASE UINT32_C(0xA0000000) 26 #define MCP_PPB_BASE_INTERNAL UINT32_C(0xE0000000) 27 #define MCP_PPB_BASE_EXTERNAL UINT32_C(0xE0040000) 28 29 /* 30 * Peripherals 31 */ 32 #define MCP_REFCLK_CNTCTL_BASE (MCP_PERIPH_BASE) 33 #define MCP_REFCLK_CNTBASE0_BASE (MCP_PERIPH_BASE + 0x1000) 34 #define MCP_UART0_BASE (MCP_PERIPH_BASE + 0x2000) 35 #define MCP_UART1_BASE (MCP_PERIPH_BASE + 0x3000) 36 #define MCP_WDOG_BASE (MCP_PERIPH_BASE + 0x6000) 37 #define MCP_MHU_AP_BASE (MCP_PERIPH_BASE + 0x400000) 38 39 /* 40 * Power control peripherals 41 */ 42 #define MCP_PIK_BASE (MCP_POWER_PERIPH_BASE) 43 44 /* 45 * System access port 1 46 */ 47 #define MCP_REFCLK_CNTCONTROL_BASE (MCP_SYS1_BASE + 0x2A430000) 48 49 /* 50 * Base addresses of MHU devices v2 51 */ 52 #define MCP_MHU_MCP_SCP_SND (MCP_MHU_SCP_BASE + 0x00000) 53 #define MCP_MHU_MCP_SCP_RCV (MCP_MHU_SCP_BASE + 0x10000) 54 55 #endif /* MCP_RDN1E1_MMAP_H */ 56