1 /* 2 * Arm SCP/MCP Software 3 * Copyright (c) 2017-2021, Arm Limited and Contributors. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef RDN1E1_PIK_CPU_H 9 #define RDN1E1_PIK_CPU_H 10 11 #include <fwk_macros.h> 12 13 #include <stdint.h> 14 15 /*! 16 * \brief PE Static Configuration register definitions 17 */ 18 struct static_config_reg { 19 FWK_RW uint32_t STATIC_CONFIG; 20 FWK_RW uint32_t RVBARADDR_LW; 21 FWK_RW uint32_t RVBARADDR_UP; 22 uint32_t RESERVED; 23 }; 24 25 /*! 26 * \brief AP cores clock control register definitions 27 */ 28 struct coreclk_reg { 29 FWK_RW uint32_t CTRL; 30 FWK_RW uint32_t DIV; 31 uint32_t RESERVED; 32 FWK_RW uint32_t MOD; 33 }; 34 35 /*! 36 * \brief CPU (V8.2) PIK register definitions 37 */ 38 struct pik_cpu_reg { 39 FWK_RW uint32_t CLUSTER_CONFIG; 40 uint8_t RESERVED0[0x10 - 0x4]; 41 struct static_config_reg STATIC_CONFIG[16]; 42 uint8_t RESERVED1[0x800 - 0x110]; 43 FWK_RW uint32_t PPUCLK_CTRL; 44 FWK_RW uint32_t PPUCLK_DIV1; 45 uint8_t RESERVED2[0x810 - 0x808]; 46 FWK_RW uint32_t PCLK_CTRL; 47 uint8_t RESERVED3[0x820 - 0x814]; 48 FWK_RW uint32_t DBGCLK_CTRL; 49 FWK_RW uint32_t DBGCLK_DIV1; 50 uint8_t RESERVED4[0x830 - 0x828]; 51 FWK_RW uint32_t GICCLK_CTRL; 52 uint8_t RESERVED5[0x840 - 0x834]; 53 FWK_RW uint32_t AMBACLK_CTRL; 54 uint8_t RESERVED6[0x850 - 0x844]; 55 FWK_RW uint32_t CLUSCLK_CTRL; 56 FWK_RW uint32_t CLUSCLK_DIV1; 57 uint8_t RESERVED7[0x860 - 0x858]; 58 struct coreclk_reg CORECLK[8]; 59 uint8_t RESERVED8[0xA00 - 0x8E0]; 60 FWK_R uint32_t CLKFORCE_STATUS; 61 FWK_W uint32_t CLKFORCE_SET; 62 FWK_W uint32_t CLKFORCE_CLR; 63 uint8_t RESERVED9[0xB00 - 0xA0C]; 64 FWK_R uint32_t NERRIQ_INT_STATUS; 65 FWK_R uint32_t NFAULTIQ_INT_STATUS; 66 uint8_t RESERVED10[0xFB4 - 0xB08]; 67 FWK_R uint32_t CAP3; 68 FWK_R uint32_t CAP2; 69 FWK_R uint32_t CAP; 70 FWK_R uint32_t PCL_CONFIG; 71 uint8_t RESERVED11[0xFD0 - 0xFC4]; 72 FWK_R uint32_t PID4; 73 FWK_R uint32_t PID5; 74 FWK_R uint32_t PID6; 75 FWK_R uint32_t PID7; 76 FWK_R uint32_t PID0; 77 FWK_R uint32_t PID1; 78 FWK_R uint32_t PID2; 79 FWK_R uint32_t PID3; 80 FWK_R uint32_t ID0; 81 FWK_R uint32_t ID1; 82 FWK_R uint32_t ID2; 83 FWK_R uint32_t ID3; 84 }; 85 86 #define PIK_CPU_CAP_CLUSSYNC UINT32_C(0x00000001) 87 #define PIK_CPU_CAP_CORESYNC(CORE) ((uint32_t)(1 << ((CORE) + 1))) 88 #define PIK_CPU_CAP_PE_MASK UINT32_C(0xF0000000) 89 #define PIK_CPU_CAP_PE_POS 28 90 91 #define PIK_CPU_PCL_CONFIG_NO_OF_PPU UINT32_C(0x0000000F) 92 93 #endif /* RDN1E1_PIK_CPU_H */ 94