1 /*
2  * Arm SCP/MCP Software
3  * Copyright (c) 2017-2021, Arm Limited and Contributors. All rights reserved.
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 
8 #ifndef RDN1E1_PIK_SYSTEM_H
9 #define RDN1E1_PIK_SYSTEM_H
10 
11 #include <fwk_macros.h>
12 
13 #include <stdint.h>
14 
15 /*!
16  * \brief TCU clock register definitions
17  */
18 struct tcuclk_ctrl_reg {
19     FWK_RW uint32_t   TCUCLK_CTRL;
20     FWK_RW uint32_t   TCUCLK_DIV1;
21 };
22 
23 /*!
24  * \brief System PIK register definitions
25  */
26 struct pik_system_reg {
27             uint8_t         RESERVED0[0x800 - 0x0];
28     FWK_RW  uint32_t        PPUCLK_CTRL;
29     FWK_RW  uint32_t        PPUCLK_DIV1;
30             uint8_t         RESERVED1[0x820 - 0x808];
31     FWK_RW  uint32_t        INTCLK_CTRL;
32     FWK_RW  uint32_t        INTCLK_DIV1;
33             uint8_t         RESERVED2[0x830 - 0x828];
34     struct tcuclk_ctrl_reg  TCUCLK[4];
35     FWK_RW  uint32_t        GICCLK_CTRL;
36     FWK_RW  uint32_t        GICCLK_DIV1;
37             uint8_t         RESERVED3[0x860 - 0x858];
38     FWK_RW  uint32_t        PCLKSCP_CTRL;
39     FWK_RW  uint32_t        PCLKSCP_DIV1;
40             uint8_t         RESERVED4[0x870 - 0x868];
41     FWK_RW  uint32_t        SYSPERCLK_CTRL;
42     FWK_RW  uint32_t        SYSPERCLK_DIV1;
43             uint8_t         RESERVED5[0x880 - 0x878];
44     FWK_RW  uint32_t        DMCCLK_CTRL;
45     FWK_RW  uint32_t        DMCCLK_DIV1;
46             uint8_t         RESERVED6[0x890 - 0x888];
47     FWK_RW  uint32_t        SYSPCLKDBG_CTRL;
48     FWK_RW  uint32_t        SYSPCLKDBG_DIV1;
49             uint8_t         RESERVED7[0x8A0 - 0x898];
50     FWK_RW  uint32_t        UARTCLK_CTRL;
51     FWK_RW  uint32_t        UARTCLK_DIV1;
52             uint8_t         RESERVED8[0xA00 - 0x8A8];
53     FWK_R   uint32_t        CLKFORCE_STATUS;
54     FWK_W   uint32_t        CLKFORCE_SET;
55     FWK_W   uint32_t        CLKFORCE_CLR;
56             uint8_t         RESERVED9[0xB0C - 0xA0C];
57     FWK_RW  uint32_t        SYSTOP_RST_DLY;
58             uint8_t         RESERVED10[0xFC0 - 0xB10];
59     FWK_R   uint32_t        PCL_CONFIG;
60             uint8_t         RESERVED11[0xFD0 - 0xFC4];
61     FWK_R   uint32_t        PID4;
62     FWK_R   uint32_t        PID5;
63     FWK_R   uint32_t        PID6;
64     FWK_R   uint32_t        PID7;
65     FWK_R   uint32_t        PID0;
66     FWK_R   uint32_t        PID1;
67     FWK_R   uint32_t        PID2;
68     FWK_R   uint32_t        PID3;
69     FWK_R   uint32_t        ID0;
70     FWK_R   uint32_t        ID1;
71     FWK_R   uint32_t        ID2;
72     FWK_R   uint32_t        ID3;
73 };
74 
75 #endif  /* RDN1E1_PIK_SYSTEM_H */
76