1 /*
2  * Arm SCP/MCP Software
3  * Copyright (c) 2020-2022, Arm Limited and Contributors. All rights reserved.
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 
8 #ifndef CLOCK_SOC_H
9 #define CLOCK_SOC_H
10 
11 #include "platform_core.h"
12 
13 #include <fwk_macros.h>
14 
15 #if (PLATFORM_VARIANT == 3)
16 #    define CLOCK_RATE_REFCLK (125UL * FWK_MHZ)
17 #else
18 #    define CLOCK_RATE_REFCLK (100UL * FWK_MHZ)
19 #endif
20 
21 #define CLOCK_RATE_SYSPLLCLK (2000UL * FWK_MHZ)
22 
23 #if (PLATFORM_VARIANT == 3)
24 /* Macro definitions of Reference Clock Control register. */
25 #    define REFCLK_CTRL_CLKSELECT_REFCLK_100 0x1
26 #    define REFCLK_CTRL_CLKSELECT_REFCLK_125 0x2
27 #    define REFCLK_CTRL_CLKSELECT_CUR_MASK   0xff00
28 #    define REFCLK_CTRL_CLKSELECT_CUR_SHIFT  8
29 
30 /*
31  * CNTINCR register specifies the increment step value for the system counter on
32  * each clock tick. This register is at offset 0xD0 from the base of the
33  * CNTControlBase register frame.
34  */
35 #    define REFCLK_CNTINCR 0xD0
36 #endif
37 
38 /*
39  * PLL clock indexes.
40  */
41 enum clock_pll_idx {
42     CLOCK_PLL_IDX_CPU0,
43     CLOCK_PLL_IDX_CPU1,
44     CLOCK_PLL_IDX_CPU2,
45     CLOCK_PLL_IDX_CPU3,
46 #if (NUMBER_OF_CLUSTERS > 4)
47     CLOCK_PLL_IDX_CPU4,
48     CLOCK_PLL_IDX_CPU5,
49     CLOCK_PLL_IDX_CPU6,
50     CLOCK_PLL_IDX_CPU7,
51 #    if (NUMBER_OF_CLUSTERS > 8)
52     CLOCK_PLL_IDX_CPU8,
53     CLOCK_PLL_IDX_CPU9,
54     CLOCK_PLL_IDX_CPU10,
55     CLOCK_PLL_IDX_CPU11,
56     CLOCK_PLL_IDX_CPU12,
57     CLOCK_PLL_IDX_CPU13,
58     CLOCK_PLL_IDX_CPU14,
59     CLOCK_PLL_IDX_CPU15,
60 #    endif
61 #endif
62     CLOCK_PLL_IDX_SYS,
63     CLOCK_PLL_IDX_DMC,
64     CLOCK_PLL_IDX_INTERCONNECT,
65     CLOCK_PLL_IDX_COUNT
66 };
67 
68 /*
69  * PIK clock indexes.
70  */
71 enum clock_pik_idx {
72     CLOCK_PIK_IDX_CLUS0_CPU0,
73     CLOCK_PIK_IDX_CLUS1_CPU0,
74     CLOCK_PIK_IDX_CLUS2_CPU0,
75     CLOCK_PIK_IDX_CLUS3_CPU0,
76 #if (NUMBER_OF_CLUSTERS > 4)
77     CLOCK_PIK_IDX_CLUS4_CPU0,
78     CLOCK_PIK_IDX_CLUS5_CPU0,
79     CLOCK_PIK_IDX_CLUS6_CPU0,
80     CLOCK_PIK_IDX_CLUS7_CPU0,
81 #    if (NUMBER_OF_CLUSTERS > 8)
82     CLOCK_PIK_IDX_CLUS8_CPU0,
83     CLOCK_PIK_IDX_CLUS9_CPU0,
84     CLOCK_PIK_IDX_CLUS10_CPU0,
85     CLOCK_PIK_IDX_CLUS11_CPU0,
86     CLOCK_PIK_IDX_CLUS12_CPU0,
87     CLOCK_PIK_IDX_CLUS13_CPU0,
88     CLOCK_PIK_IDX_CLUS14_CPU0,
89     CLOCK_PIK_IDX_CLUS15_CPU0,
90 #    endif
91 #endif
92     CLOCK_PIK_IDX_DMC,
93     CLOCK_PIK_IDX_INTERCONNECT,
94     CLOCK_PIK_IDX_SCP,
95     CLOCK_PIK_IDX_GIC,
96     CLOCK_PIK_IDX_PCLKSCP,
97     CLOCK_PIK_IDX_SYSPERCLK,
98     CLOCK_PIK_IDX_UARTCLK,
99     CLOCK_PIK_IDX_COUNT
100 };
101 
102 /*
103  * CSS clock indexes.
104  */
105 enum clock_css_idx {
106     CLOCK_CSS_IDX_CPU_GROUP0,
107     CLOCK_CSS_IDX_CPU_GROUP1,
108     CLOCK_CSS_IDX_CPU_GROUP2,
109     CLOCK_CSS_IDX_CPU_GROUP3,
110 #if (NUMBER_OF_CLUSTERS > 4)
111     CLOCK_CSS_IDX_CPU_GROUP4,
112     CLOCK_CSS_IDX_CPU_GROUP5,
113     CLOCK_CSS_IDX_CPU_GROUP6,
114     CLOCK_CSS_IDX_CPU_GROUP7,
115 #    if (NUMBER_OF_CLUSTERS > 8)
116     CLOCK_CSS_IDX_CPU_GROUP8,
117     CLOCK_CSS_IDX_CPU_GROUP9,
118     CLOCK_CSS_IDX_CPU_GROUP10,
119     CLOCK_CSS_IDX_CPU_GROUP11,
120     CLOCK_CSS_IDX_CPU_GROUP12,
121     CLOCK_CSS_IDX_CPU_GROUP13,
122     CLOCK_CSS_IDX_CPU_GROUP14,
123     CLOCK_CSS_IDX_CPU_GROUP15,
124 #    endif
125 #endif
126     CLOCK_CSS_IDX_COUNT
127 };
128 
129 /*
130  * Clock indexes.
131  */
132 enum clock_idx {
133     CLOCK_IDX_CPU_GROUP0,
134     CLOCK_IDX_CPU_GROUP1,
135     CLOCK_IDX_CPU_GROUP2,
136     CLOCK_IDX_CPU_GROUP3,
137 #if (NUMBER_OF_CLUSTERS > 4)
138     CLOCK_IDX_CPU_GROUP4,
139     CLOCK_IDX_CPU_GROUP5,
140     CLOCK_IDX_CPU_GROUP6,
141     CLOCK_IDX_CPU_GROUP7,
142 #    if (NUMBER_OF_CLUSTERS > 8)
143     CLOCK_IDX_CPU_GROUP8,
144     CLOCK_IDX_CPU_GROUP9,
145     CLOCK_IDX_CPU_GROUP10,
146     CLOCK_IDX_CPU_GROUP11,
147     CLOCK_IDX_CPU_GROUP12,
148     CLOCK_IDX_CPU_GROUP13,
149     CLOCK_IDX_CPU_GROUP14,
150     CLOCK_IDX_CPU_GROUP15,
151 #    endif
152 #endif
153     CLOCK_IDX_INTERCONNECT,
154     CLOCK_IDX_COUNT
155 };
156 
157 #endif /* CLOCK_SOC_H */
158