1 /* 2 * Arm SCP/MCP Software 3 * Copyright (c) 2020-2022, Arm Limited and Contributors. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef SCP_SOC_MMAP_H 9 #define SCP_SOC_MMAP_H 10 11 #include "platform_core.h" 12 #include "scp_mmap.h" 13 14 #define SCP_NOR0_FLASH_BASE (SCP_SOC_EXPANSION1_BASE + 0x07000000) 15 16 #define SCP_PLL_BASE (SCP_SOC_EXPANSION3_BASE + 0x03000000) 17 18 #define SCP_PLL_SYSPLL (SCP_PLL_BASE + 0x00000000) 19 #define SCP_PLL_DMC (SCP_PLL_BASE + 0x00000010) 20 #define SCP_PLL_INTERCONNECT (SCP_PLL_BASE + 0x00000020) 21 #define SCP_PLL_STATUS0 (SCP_PLL_BASE + 0x00000180) 22 #define SCP_PLL_STATUS1 (SCP_PLL_BASE + 0x00000184) 23 24 #define SCP_PLL_CPU0 (SCP_PLL_BASE + 0x00000100) 25 #define SCP_PLL_CPU1 (SCP_PLL_BASE + 0x00000104) 26 #define SCP_PLL_CPU2 (SCP_PLL_BASE + 0x00000108) 27 #define SCP_PLL_CPU3 (SCP_PLL_BASE + 0x0000010C) 28 #if (NUMBER_OF_CLUSTERS > 4) 29 # define SCP_PLL_CPU4 (SCP_PLL_BASE + 0x00000110) 30 # define SCP_PLL_CPU5 (SCP_PLL_BASE + 0x00000114) 31 # define SCP_PLL_CPU6 (SCP_PLL_BASE + 0x00000118) 32 # define SCP_PLL_CPU7 (SCP_PLL_BASE + 0x0000011C) 33 # if (NUMBER_OF_CLUSTERS > 8) 34 # define SCP_PLL_CPU8 (SCP_PLL_BASE + 0x00000120) 35 # define SCP_PLL_CPU9 (SCP_PLL_BASE + 0x00000124) 36 # define SCP_PLL_CPU10 (SCP_PLL_BASE + 0x00000128) 37 # define SCP_PLL_CPU11 (SCP_PLL_BASE + 0x0000012c) 38 # define SCP_PLL_CPU12 (SCP_PLL_BASE + 0x00000130) 39 # define SCP_PLL_CPU13 (SCP_PLL_BASE + 0x00000134) 40 # define SCP_PLL_CPU14 (SCP_PLL_BASE + 0x00000138) 41 # define SCP_PLL_CPU15 (SCP_PLL_BASE + 0x0000013C) 42 # endif 43 #endif 44 45 /* PCIe ECAM and MMIO addresses */ 46 #define AP_PCIE_ECAM_BASE (0x1010000000ULL) 47 #define AP_PCIE_MMIOL_BASE (0x60000000) 48 #define AP_PCIE_MMIOH_BASE (0x4000000000ULL) 49 50 #endif /* SCP_SOC_MMAP_H */ 51