1 /*
2  * Arm SCP/MCP Software
3  * Copyright (c) 2020-2021, Arm Limited and Contributors. All rights reserved.
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 
8 #ifndef CLOCK_SOC_H
9 #define CLOCK_SOC_H
10 
11 #include <fwk_macros.h>
12 
13 #define CLOCK_RATE_REFCLK    (100UL * FWK_MHZ)
14 #define CLOCK_RATE_SYSPLLCLK (2000UL * FWK_MHZ)
15 
16 /*
17  * PLL clock indexes.
18  */
19 enum clock_pll_idx {
20     CLOCK_PLL_IDX_CPU0,
21     CLOCK_PLL_IDX_CPU1,
22     CLOCK_PLL_IDX_CPU2,
23     CLOCK_PLL_IDX_CPU3,
24     CLOCK_PLL_IDX_CPU4,
25     CLOCK_PLL_IDX_CPU5,
26     CLOCK_PLL_IDX_CPU6,
27     CLOCK_PLL_IDX_CPU7,
28     CLOCK_PLL_IDX_CPU8,
29     CLOCK_PLL_IDX_CPU9,
30     CLOCK_PLL_IDX_CPU10,
31     CLOCK_PLL_IDX_CPU11,
32     CLOCK_PLL_IDX_CPU12,
33     CLOCK_PLL_IDX_CPU13,
34     CLOCK_PLL_IDX_CPU14,
35     CLOCK_PLL_IDX_CPU15,
36     CLOCK_PLL_IDX_SYS,
37     CLOCK_PLL_IDX_DMC,
38     CLOCK_PLL_IDX_INTERCONNECT,
39     CLOCK_PLL_IDX_COUNT
40 };
41 
42 /*
43  * PIK clock indexes.
44  */
45 enum clock_pik_idx {
46     CLOCK_PIK_IDX_CLUS0_CPU0,
47     CLOCK_PIK_IDX_CLUS1_CPU0,
48     CLOCK_PIK_IDX_CLUS2_CPU0,
49     CLOCK_PIK_IDX_CLUS3_CPU0,
50     CLOCK_PIK_IDX_CLUS4_CPU0,
51     CLOCK_PIK_IDX_CLUS5_CPU0,
52     CLOCK_PIK_IDX_CLUS6_CPU0,
53     CLOCK_PIK_IDX_CLUS7_CPU0,
54     CLOCK_PIK_IDX_CLUS8_CPU0,
55     CLOCK_PIK_IDX_CLUS9_CPU0,
56     CLOCK_PIK_IDX_CLUS10_CPU0,
57     CLOCK_PIK_IDX_CLUS11_CPU0,
58     CLOCK_PIK_IDX_CLUS12_CPU0,
59     CLOCK_PIK_IDX_CLUS13_CPU0,
60     CLOCK_PIK_IDX_CLUS14_CPU0,
61     CLOCK_PIK_IDX_CLUS15_CPU0,
62     CLOCK_PIK_IDX_DMC,
63     CLOCK_PIK_IDX_INTERCONNECT,
64     CLOCK_PIK_IDX_SCP,
65     CLOCK_PIK_IDX_GIC,
66     CLOCK_PIK_IDX_PCLKSCP,
67     CLOCK_PIK_IDX_SYSPERCLK,
68     CLOCK_PIK_IDX_UARTCLK,
69     CLOCK_PIK_IDX_COUNT
70 };
71 
72 /*
73  * CSS clock indexes.
74  */
75 enum clock_css_idx {
76     CLOCK_CSS_IDX_CPU_GROUP0,
77     CLOCK_CSS_IDX_CPU_GROUP1,
78     CLOCK_CSS_IDX_CPU_GROUP2,
79     CLOCK_CSS_IDX_CPU_GROUP3,
80     CLOCK_CSS_IDX_CPU_GROUP4,
81     CLOCK_CSS_IDX_CPU_GROUP5,
82     CLOCK_CSS_IDX_CPU_GROUP6,
83     CLOCK_CSS_IDX_CPU_GROUP7,
84     CLOCK_CSS_IDX_CPU_GROUP8,
85     CLOCK_CSS_IDX_CPU_GROUP9,
86     CLOCK_CSS_IDX_CPU_GROUP10,
87     CLOCK_CSS_IDX_CPU_GROUP11,
88     CLOCK_CSS_IDX_CPU_GROUP12,
89     CLOCK_CSS_IDX_CPU_GROUP13,
90     CLOCK_CSS_IDX_CPU_GROUP14,
91     CLOCK_CSS_IDX_CPU_GROUP15,
92     CLOCK_CSS_IDX_COUNT
93 };
94 
95 /*
96  * Clock indexes.
97  */
98 enum clock_idx {
99     CLOCK_IDX_INTERCONNECT,
100     CLOCK_IDX_CPU_GROUP0,
101     CLOCK_IDX_CPU_GROUP1,
102     CLOCK_IDX_CPU_GROUP2,
103     CLOCK_IDX_CPU_GROUP3,
104     CLOCK_IDX_CPU_GROUP4,
105     CLOCK_IDX_CPU_GROUP5,
106     CLOCK_IDX_CPU_GROUP6,
107     CLOCK_IDX_CPU_GROUP7,
108     CLOCK_IDX_CPU_GROUP8,
109     CLOCK_IDX_CPU_GROUP9,
110     CLOCK_IDX_CPU_GROUP10,
111     CLOCK_IDX_CPU_GROUP11,
112     CLOCK_IDX_CPU_GROUP12,
113     CLOCK_IDX_CPU_GROUP13,
114     CLOCK_IDX_CPU_GROUP14,
115     CLOCK_IDX_CPU_GROUP15,
116     CLOCK_IDX_COUNT
117 };
118 
119 #endif /* CLOCK_SOC_H */
120