1 /*
2  * Arm SCP/MCP Software
3  * Copyright (c) 2020-2021, Arm Limited and Contributors. All rights reserved.
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 
8 #ifndef CLOCK_SOC_H
9 #define CLOCK_SOC_H
10 
11 #include <fwk_macros.h>
12 
13 #define CLOCK_RATE_REFCLK    (100UL * FWK_MHZ)
14 #define CLOCK_RATE_SYSPLLCLK (2000UL * FWK_MHZ)
15 
16 /*
17  * PLL clock indexes.
18  */
19 enum clock_pll_idx {
20     CLOCK_PLL_IDX_CPU0,
21     CLOCK_PLL_IDX_CPU1,
22     CLOCK_PLL_IDX_CPU2,
23     CLOCK_PLL_IDX_CPU3,
24     CLOCK_PLL_IDX_SYS,
25     CLOCK_PLL_IDX_DMC,
26     CLOCK_PLL_IDX_INTERCONNECT,
27     CLOCK_PLL_IDX_COUNT
28 };
29 
30 /*
31  * PIK clock indexes.
32  */
33 enum clock_pik_idx {
34     CLOCK_PIK_IDX_CLUS0_CPU0,
35     CLOCK_PIK_IDX_CLUS1_CPU0,
36     CLOCK_PIK_IDX_CLUS2_CPU0,
37     CLOCK_PIK_IDX_CLUS3_CPU0,
38     CLOCK_PIK_IDX_DMC,
39     CLOCK_PIK_IDX_INTERCONNECT,
40     CLOCK_PIK_IDX_SCP,
41     CLOCK_PIK_IDX_GIC,
42     CLOCK_PIK_IDX_PCLKSCP,
43     CLOCK_PIK_IDX_SYSPERCLK,
44     CLOCK_PIK_IDX_UARTCLK,
45     CLOCK_PIK_IDX_COUNT
46 };
47 
48 /*
49  * CSS clock indexes.
50  */
51 enum clock_css_idx {
52     CLOCK_CSS_IDX_CPU_GROUP0,
53     CLOCK_CSS_IDX_CPU_GROUP1,
54     CLOCK_CSS_IDX_CPU_GROUP2,
55     CLOCK_CSS_IDX_CPU_GROUP3,
56     CLOCK_CSS_IDX_COUNT
57 };
58 
59 /*
60  * Clock indexes.
61  */
62 enum clock_idx {
63     CLOCK_IDX_INTERCONNECT,
64     CLOCK_IDX_CPU_GROUP0,
65     CLOCK_IDX_CPU_GROUP1,
66     CLOCK_IDX_CPU_GROUP2,
67     CLOCK_IDX_CPU_GROUP3,
68     CLOCK_IDX_COUNT
69 };
70 
71 #endif /* CLOCK_SOC_H */
72