1 /*
2  * Arm SCP/MCP Software
3  * Copyright (c) 2020-2022, Arm Limited and Contributors. All rights reserved.
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 
8 #ifndef FMW_CMSIS_H
9 #define FMW_CMSIS_H
10 
11 #include <stdint.h>
12 
13 #define __CHECK_DEVICE_DEFINES
14 #define __CM7_REV              0x0000U
15 #define __FPU_PRESENT          0U
16 #define __MPU_PRESENT          1U
17 #define __ICACHE_PRESENT       0U
18 #define __DCACHE_PRESENT       0U
19 #define __DTCM_PRESENT         0U
20 #define __NVIC_PRIO_BITS       3U
21 #define __Vendor_SysTickConfig 0U
22 #define __VTOR_PRESENT         1U
23 
24 extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock)*/
25 
26 typedef enum IRQn {
27     Reset_IRQn = -15,
28     NonMaskableInt_IRQn = -14,
29     HardFault_IRQn = -13,
30     MemoryManagement_IRQn = -12,
31     BusFault_IRQn = -11,
32     UsageFault_IRQn = -10,
33     SVCall_IRQn = -5,
34     DebugMonitor_IRQn = -4,
35     PendSV_IRQn = -2,
36     SysTick_IRQn = -1,
37 
38     SOC_WAKEUP0_IRQ = 16, /* SoC Expansion Wakeup */
39     TIMREFCLK_IRQ = 33, /* REFCLK Physical Timer */
40     PPU_CORES0_IRQ =
41         50, /* Consolidated PPU Interrupt for cores 1-32, 129-160 */
42     PPU_CORES1_IRQ =
43         51, /* Consolidated PPU Interrupt for cores 33-64, 161-192 */
44     PPU_CORES2_IRQ =
45         52, /* Consolidated PPU Interrupt for cores 65-96, 193-224 */
46     PPU_CORES3_IRQ =
47         53, /* Consolidated PPU Interrupt for cores 97-128, 225-256 */
48     PPU_CLUSTERS_IRQ = 54, /* Consolidated clusters PPU */
49     MHU_AP_SEC_IRQ = 83, /* MHU secure IRQ between SCP and AP */
50 
51     IRQn_MAX = INT16_MAX,
52 } IRQn_Type;
53 
54 #include <core_cm7.h>
55 
56 #endif /* FMW_CMSIS_H */
57