1 /*
2  * Arm SCP/MCP Software
3  * Copyright (c) 2020-2021, Arm Limited and Contributors. All rights reserved.
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 
8 #ifndef SYSTEM_PIK_H
9 #define SYSTEM_PIK_H
10 
11 #include "scp_css_mmap.h"
12 
13 #include <fwk_macros.h>
14 
15 #include <stdint.h>
16 
17 /*!
18  * \brief TCU clock register definitions
19  */
20 struct tcuclk_ctrl_reg {
21     FWK_RW uint32_t   TCUCLK_CTRL;
22     FWK_RW uint32_t   TCUCLK_DIV1;
23 };
24 
25 /*!
26  * \brief System PIK register definitions
27  */
28 struct pik_system_reg {
29             uint8_t         RESERVED0[0x800 - 0x0];
30     FWK_RW  uint32_t        PPUCLK_CTRL;
31     FWK_RW  uint32_t        PPUCLK_DIV1;
32             uint8_t         RESERVED1[0x820 - 0x808];
33     FWK_RW  uint32_t        INTCLK_CTRL;
34     FWK_RW  uint32_t        INTCLK_DIV1;
35             uint8_t         RESERVED2[0x830 - 0x828];
36     struct tcuclk_ctrl_reg  TCUCLK[4];
37     FWK_RW  uint32_t        GICCLK_CTRL;
38     FWK_RW  uint32_t        GICCLK_DIV1;
39             uint8_t         RESERVED3[0x860 - 0x858];
40     FWK_RW  uint32_t        PCLKSCP_CTRL;
41     FWK_RW  uint32_t        PCLKSCP_DIV1;
42             uint8_t         RESERVED4[0x870 - 0x868];
43     FWK_RW  uint32_t        SYSPERCLK_CTRL;
44     FWK_RW  uint32_t        SYSPERCLK_DIV1;
45             uint8_t         RESERVED5[0x880 - 0x878];
46     FWK_RW  uint32_t        DMCCLK_CTRL;
47     FWK_RW  uint32_t        DMCCLK_DIV1;
48             uint8_t         RESERVED6[0x890 - 0x888];
49     FWK_RW  uint32_t        SYSPCLKDBG_CTRL;
50     FWK_RW  uint32_t        SYSPCLKDBG_DIV1;
51             uint8_t         RESERVED7[0x8A0 - 0x898];
52     FWK_RW  uint32_t        UARTCLK_CTRL;
53     FWK_RW  uint32_t        UARTCLK_DIV1;
54             uint8_t         RESERVED8[0xA00 - 0x8A8];
55     FWK_R   uint32_t        CLKFORCE_STATUS;
56     FWK_W   uint32_t        CLKFORCE_SET;
57     FWK_W   uint32_t        CLKFORCE_CLR;
58             uint8_t         RESERVED9[0xB0C - 0xA0C];
59     FWK_RW  uint32_t        SYSTOP_RST_DLY;
60             uint8_t         RESERVED10[0xFC0 - 0xB10];
61     FWK_R   uint32_t        PCL_CONFIG;
62             uint8_t         RESERVED11[0xFD0 - 0xFC4];
63     FWK_R   uint32_t        PID4;
64     FWK_R   uint32_t        PID5;
65     FWK_R   uint32_t        PID6;
66     FWK_R   uint32_t        PID7;
67     FWK_R   uint32_t        PID0;
68     FWK_R   uint32_t        PID1;
69     FWK_R   uint32_t        PID2;
70     FWK_R   uint32_t        PID3;
71     FWK_R   uint32_t        ID0;
72     FWK_R   uint32_t        ID1;
73     FWK_R   uint32_t        ID2;
74     FWK_R   uint32_t        ID3;
75 };
76 
77 #define SYSTEM_PIK_PTR ((struct pik_system_reg *)SCP_PIK_SYSTEM_BASE)
78 
79 #endif /* SYSTEM_PIK_H */
80