1 /* 2 * Arm SCP/MCP Software 3 * Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef SCP_SYSTEM_MMAP_H 9 #define SCP_SYSTEM_MMAP_H 10 11 #include "scp_sgi575_mmap.h" 12 13 #define SCP_PLAT_BASE (SCP_SYS0_BASE + 0x3FFE0000) 14 15 #define SCP_PLL_BASE (SCP_EXPANSION3_BASE + 0x03000000) 16 17 #define SCP_PLL_SYSPLL (SCP_PLL_BASE) 18 #define SCP_PLL_CLUS0 (SCP_PLL_BASE + 0x00000004) 19 #define SCP_PLL_CLUS1 (SCP_PLL_BASE + 0x00000008) 20 #define SCP_PLL_DMC (SCP_PLL_BASE + 0x00000010) 21 #define SCP_PLL_INTERCONNECT (SCP_PLL_BASE + 0x00000020) 22 23 #define SCP_PLL_CPU0 (SCP_PLL_BASE + 0x00000100) 24 #define SCP_PLL_CPU1 (SCP_PLL_BASE + 0x00000104) 25 #define SCP_PLL_CPU2 (SCP_PLL_BASE + 0x00000108) 26 #define SCP_PLL_CPU3 (SCP_PLL_BASE + 0x0000010C) 27 #define SCP_PLL_CPU4 (SCP_PLL_BASE + 0x00000110) 28 #define SCP_PLL_CPU5 (SCP_PLL_BASE + 0x00000114) 29 #define SCP_PLL_CPU6 (SCP_PLL_BASE + 0x00000118) 30 #define SCP_PLL_CPU7 (SCP_PLL_BASE + 0x0000011C) 31 32 #define SCP_DDR_PHY0 (SCP_SYS0_BASE + 0x3FB60000) 33 #define SCP_DDR_PHY1 (SCP_SYS0_BASE + 0x3FB70000) 34 35 #define SCP_DMC0 (SCP_MEMORY_CONTROLLER + 0x00000000) 36 #define SCP_DMC1 (SCP_MEMORY_CONTROLLER + 0x00100000) 37 38 #define SCP_SENSOR_SOC_TEMP (SCP_PLAT_BASE + 0x00000080) 39 #define SCP_PLATFORM_ID (SCP_PLAT_BASE + 0x000000E0) 40 41 #endif /* SCP_SYSTEM_MMAP_H*/ 42