1 /* 2 * Arm SCP/MCP Software 3 * Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef CONFIG_CLOCK_H 9 #define CONFIG_CLOCK_H 10 11 /* 12 * Clock indexes. 13 */ 14 enum clock_idx { 15 CLOCK_IDX_INTERCONNECT, 16 CLOCK_IDX_CPU_GROUP0, 17 CLOCK_IDX_CPU_GROUP1, 18 CLOCK_IDX_COUNT 19 }; 20 21 /* 22 * PIK clock indexes. 23 */ 24 enum clock_pik_idx { 25 CLOCK_PIK_IDX_CLUS0_CPU0, 26 CLOCK_PIK_IDX_CLUS0_CPU1, 27 CLOCK_PIK_IDX_CLUS0_CPU2, 28 CLOCK_PIK_IDX_CLUS0_CPU3, 29 CLOCK_PIK_IDX_CLUS1_CPU0, 30 CLOCK_PIK_IDX_CLUS1_CPU1, 31 CLOCK_PIK_IDX_CLUS1_CPU2, 32 CLOCK_PIK_IDX_CLUS1_CPU3, 33 CLOCK_PIK_IDX_DMC, 34 CLOCK_PIK_IDX_INTERCONNECT, 35 CLOCK_PIK_IDX_SCP, 36 CLOCK_PIK_IDX_GIC, 37 CLOCK_PIK_IDX_PCLKSCP, 38 CLOCK_PIK_IDX_SYSPERCLK, 39 CLOCK_PIK_IDX_UARTCLK, 40 CLOCK_PIK_IDX_COUNT 41 }; 42 43 /* 44 * CSS clock indexes. 45 */ 46 enum clock_css_idx { 47 CLOCK_CSS_IDX_CPU_GROUP0, 48 CLOCK_CSS_IDX_CPU_GROUP1, 49 CLOCK_CSS_IDX_COUNT 50 }; 51 52 /* 53 * PLL clock indexes. 54 */ 55 enum clock_pll_idx { 56 CLOCK_PLL_IDX_CPU0, 57 CLOCK_PLL_IDX_CPU1, 58 CLOCK_PLL_IDX_SYS, 59 CLOCK_PLL_IDX_DMC, 60 CLOCK_PLL_IDX_INTERCONNECT, 61 CLOCK_PLL_IDX_COUNT 62 }; 63 64 #endif /* CONFIG_CLOCK_H */ 65