1 /*
2 * Arm SCP/MCP Software
3 * Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #include "config_clock.h"
9 #include "scp_sgi575_pik.h"
10 #include "scp_system_mmap.h"
11 #include "sgi575_pik_scp.h"
12
13 #include <mod_system_pll.h>
14
15 #include <fwk_element.h>
16 #include <fwk_id.h>
17 #include <fwk_macros.h>
18 #include <fwk_module.h>
19
20 static const struct fwk_element system_pll_element_table[] = {
21 [CLOCK_PLL_IDX_CPU0] = {
22 .name = "CPU_PLL_0",
23 .data = &((struct mod_system_pll_dev_config) {
24 .control_reg = (void *)SCP_PLL_CPU0,
25 .status_reg = (void *)&PIK_SCP->PLL_STATUS[1],
26 .lock_flag_mask = PLL_STATUS_CPUPLLLOCK(0),
27 .initial_rate = 2600 * FWK_MHZ,
28 .min_rate = MOD_SYSTEM_PLL_MIN_RATE,
29 .max_rate = MOD_SYSTEM_PLL_MAX_RATE,
30 .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL,
31 }),
32 },
33 [CLOCK_PLL_IDX_CPU1] = {
34 .name = "CPU_PLL_1",
35 .data = &((struct mod_system_pll_dev_config) {
36 .control_reg = (void *)SCP_PLL_CPU1,
37 .status_reg = (void *)&PIK_SCP->PLL_STATUS[1],
38 .lock_flag_mask = PLL_STATUS_CPUPLLLOCK(1),
39 .initial_rate = 2600 * FWK_MHZ,
40 .min_rate = MOD_SYSTEM_PLL_MIN_RATE,
41 .max_rate = MOD_SYSTEM_PLL_MAX_RATE,
42 .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL,
43 }),
44 },
45 [CLOCK_PLL_IDX_SYS] = {
46 .name = "SYS_PLL",
47 .data = &((struct mod_system_pll_dev_config) {
48 .control_reg = (void *)SCP_PLL_SYSPLL,
49 .status_reg = (void *)&PIK_SCP->PLL_STATUS[0],
50 .lock_flag_mask = PLL_STATUS_0_SYSPLLLOCK,
51 .initial_rate = 2000 * FWK_MHZ,
52 .min_rate = MOD_SYSTEM_PLL_MIN_RATE,
53 .max_rate = MOD_SYSTEM_PLL_MAX_RATE,
54 .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL,
55 }),
56 },
57 [CLOCK_PLL_IDX_DMC] = {
58 .name = "DMC_PLL",
59 .data = &((struct mod_system_pll_dev_config) {
60 .control_reg = (void *)SCP_PLL_DMC,
61 .status_reg = (void *)&PIK_SCP->PLL_STATUS[0],
62 .lock_flag_mask = PLL_STATUS_0_DDRPLLLOCK,
63 .initial_rate = 1600 * FWK_MHZ,
64 .min_rate = MOD_SYSTEM_PLL_MIN_RATE,
65 .max_rate = MOD_SYSTEM_PLL_MAX_RATE,
66 .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL,
67 }),
68 },
69 [CLOCK_PLL_IDX_INTERCONNECT] = {
70 .name = "INT_PLL",
71 .data = &((struct mod_system_pll_dev_config) {
72 .control_reg = (void *)SCP_PLL_INTERCONNECT,
73 .status_reg = (void *)&PIK_SCP->PLL_STATUS[0],
74 .lock_flag_mask = PLL_STATUS_0_INTPLLLOCK,
75 .initial_rate = 2000 * FWK_MHZ,
76 .min_rate = MOD_SYSTEM_PLL_MIN_RATE,
77 .max_rate = MOD_SYSTEM_PLL_MAX_RATE,
78 .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL,
79 }),
80 },
81 [CLOCK_PLL_IDX_COUNT] = { 0 }, /* Termination description. */
82 };
83
system_pll_get_element_table(fwk_id_t module_id)84 static const struct fwk_element *system_pll_get_element_table
85 (fwk_id_t module_id)
86 {
87 return system_pll_element_table;
88 }
89
90 const struct fwk_module_config config_system_pll = {
91 .elements = FWK_MODULE_DYNAMIC_ELEMENTS(system_pll_get_element_table),
92 };
93