1 /* 2 * Arm SCP/MCP Software 3 * Copyright (c) 2017-2021, Arm Limited and Contributors. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef SGM775_PIK_SYSTEM_H 9 #define SGM775_PIK_SYSTEM_H 10 11 #include <fwk_macros.h> 12 13 #include <stdint.h> 14 15 /*! 16 * \brief System PIK register definitions 17 */ 18 struct pik_system_reg { 19 uint8_t RESERVED0[0x800]; 20 FWK_RW uint32_t PPUCLK_CTRL; 21 FWK_RW uint32_t PPUCLK_DIV1; 22 uint32_t RESERVED1[2]; 23 FWK_RW uint32_t ACLKNCI_CTRL; 24 FWK_RW uint32_t ACLKNCI_DIV1; 25 uint32_t RESERVED2[2]; 26 FWK_RW uint32_t ACLKCCI_CTRL; 27 FWK_RW uint32_t ACLKCCI_DIV1; 28 uint32_t RESERVED3[6]; 29 FWK_RW uint32_t TCUCLK_CTRL; 30 FWK_RW uint32_t TCUCLK_DIV1; 31 uint32_t RESERVED4[2]; 32 FWK_RW uint32_t GICCLK_CTRL; 33 FWK_RW uint32_t GICCLK_DIV1; 34 uint32_t RESERVED5[2]; 35 FWK_RW uint32_t PCLKSCP_CTRL; 36 FWK_RW uint32_t PCLKSCP_DIV1; 37 uint32_t RESERVED6[2]; 38 FWK_RW uint32_t SYSPERCLK_CTRL; 39 FWK_RW uint32_t SYSPERCLK_DIV1; 40 uint32_t RESERVED7[6]; 41 FWK_RW uint32_t FCMCLK_CTRL; 42 FWK_RW uint32_t FCMCLK_DIV1; 43 uint8_t RESERVED8[0xA00 - 0x898]; 44 FWK_R uint32_t CLKFORCE_STATUS; 45 FWK_RW uint32_t CLKFORCE_SET; 46 FWK_RW uint32_t CLKFORCE_CLR; 47 uint8_t RESERVED9[0xFBC - 0xA0C]; 48 FWK_R uint32_t CAP; 49 FWK_R uint32_t PIK_CONFIG; 50 uint32_t RESERVED10[3]; 51 FWK_R uint32_t PID4; 52 FWK_R uint32_t PID5; 53 FWK_R uint32_t PID6; 54 FWK_R uint32_t PID7; 55 FWK_R uint32_t PID0; 56 FWK_R uint32_t PID1; 57 FWK_R uint32_t PID2; 58 FWK_R uint32_t PID3; 59 FWK_R uint32_t ID0; 60 FWK_R uint32_t ID1; 61 FWK_R uint32_t ID2; 62 FWK_R uint32_t ID3; 63 }; 64 65 #define CAP_GICCLK_GATING_SUPPORT UINT32_C(0x00000001) 66 #define CAP_TCUCLK_SUPPORT UINT32_C(0x00000002) 67 #define CAP_ELA_SUPPORT UINT32_C(0x00000004) 68 #define CAP_FCMCLK_SUPPORT UINT32_C(0x00000008) 69 70 #endif /* SGM775_PIK_SYSTEM_H */ 71