1 /* 2 * Arm SCP/MCP Software 3 * Copyright (c) 2015-2021, Arm Limited and Contributors. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef SYSTEM_MMAP_H 9 #define SYSTEM_MMAP_H 10 11 #include "sgm775_mmap.h" 12 13 #define DMC_EXTERNAL0 (SYS0_BASE + 0x3FBE0000) 14 #define DMC_EXTERNAL1 (SYS0_BASE + 0x3FBF0000) 15 #define DMC_EXTERNAL2 (SYS0_BASE + 0x3FC00000) 16 #define DMC_EXTERNAL3 (SYS0_BASE + 0x3FC10000) 17 18 #define BOARD_UART1_BASE (SYS0_BASE + 0x3FF70000) 19 #define PLAT_BASE (SYS0_BASE + 0x3FFE0000) 20 21 #define PLL_GPU (PLAT_BASE + 0x00000008) 22 #define PLL_SYSTEM (PLAT_BASE + 0x0000000C) 23 #define PLL_VIDEO (PLAT_BASE + 0x00000010) 24 #define PLL_DISPLAY (PLAT_BASE + 0x00000014) 25 26 #define PIX0_CONTROL (PLAT_BASE + 0x00000018) 27 #define PIX1_CONTROL (PLAT_BASE + 0x0000001C) 28 29 #define SWCLKTCK_CONTROL (PLAT_BASE + 0x00000020) 30 #define SENSOR_SOC_TEMP (PLAT_BASE + 0x00000080) 31 #define PLATFORM_ID (PLAT_BASE + 0x000000E0) 32 33 #define PLL_CLUS0_0 (PLAT_BASE + 0x00000100) 34 #define PLL_CLUS0_1 (PLAT_BASE + 0x00000104) 35 #define PLL_CLUS0_2 (PLAT_BASE + 0x00000108) 36 #define PLL_CLUS0_3 (PLAT_BASE + 0x0000010C) 37 #define PLL_CLUS0_4 (PLAT_BASE + 0x00000110) 38 #define PLL_CLUS0_5 (PLAT_BASE + 0x00000114) 39 #define PLL_CLUS0_6 (PLAT_BASE + 0x00000118) 40 #define PLL_CLUS0_7 (PLAT_BASE + 0x0000011C) 41 42 #define DDR_PHY0 (SYS0_BASE + 0x3FB60000) 43 #define DDR_PHY1 (SYS0_BASE + 0x3FB70000) 44 #define DDR_PHY2 (SYS0_BASE + 0x3FB80000) 45 #define DDR_PHY3 (SYS0_BASE + 0x3FB90000) 46 47 #define GPV_CCI_GPU1 (SYS1_BASE + 0x2A004000) 48 #define GPV_CCI_GPU0 (SYS1_BASE + 0x2A005000) 49 #define GPV_CCI_LITTLE (SYS1_BASE + 0x2A006000) 50 #define GPV_CCI_BIG (SYS1_BASE + 0x2A007000) 51 #define GPV_VPU (SYS1_BASE + 0x2A243000) 52 #define GPV_DPU0 (SYS1_BASE + 0x2A244000) 53 #define GPV_DPU1 (SYS1_BASE + 0x2A245000) 54 55 #define DMC_INTERNAL0 (SYS1_BASE + 0x2A500000) 56 #define DMC_INTERNAL1 (SYS1_BASE + 0x2A540000) 57 #define DMC_INTERNAL2 (SYS1_BASE + 0x2A580000) 58 #define DMC_INTERNAL3 (SYS1_BASE + 0x2A5C0000) 59 60 61 #endif /* SYSTEM_MMAP_H */ 62