1 /*
2 * Arm SCP/MCP Software
3 * Copyright (c) 2015-2021, Arm Limited and Contributors. All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #include "sgm775_pik.h"
9 #include "sgm775_pik_scp.h"
10 #include "system_mmap.h"
11
12 #include <mod_system_pll.h>
13
14 #include <fwk_element.h>
15 #include <fwk_id.h>
16 #include <fwk_macros.h>
17 #include <fwk_module.h>
18
19 #include <stdbool.h>
20 #include <stddef.h>
21
22 static const struct fwk_element system_pll_element_table[] = {
23 {
24 .name = "CPU_PLL_0",
25 .data = &((struct mod_system_pll_dev_config) {
26 .control_reg = (void *)PLL_CLUS0_0,
27 .status_reg = (void *)&PIK_SCP->PLL_STATUS1,
28 .lock_flag_mask = PLL_STATUS1_CPUPLLLOCK(0, 0),
29 .initial_rate = 1330 * FWK_MHZ,
30 .min_rate = MOD_SYSTEM_PLL_MIN_RATE,
31 .max_rate = MOD_SYSTEM_PLL_MAX_RATE,
32 .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL,
33 .defer_initialization = false,
34 }),
35 },
36 {
37 .name = "CPU_PLL_1",
38 .data = &((struct mod_system_pll_dev_config) {
39 .control_reg = (void *)PLL_CLUS0_1,
40 .status_reg = (void *)&PIK_SCP->PLL_STATUS1,
41 .lock_flag_mask = PLL_STATUS1_CPUPLLLOCK(0, 1),
42 .initial_rate = 1750 * FWK_MHZ,
43 .min_rate = MOD_SYSTEM_PLL_MIN_RATE,
44 .max_rate = MOD_SYSTEM_PLL_MAX_RATE,
45 .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL,
46 .defer_initialization = false,
47 }),
48 },
49 {
50 .name = "GPU_PLL",
51 .data = &((struct mod_system_pll_dev_config) {
52 .control_reg = (void *)PLL_GPU,
53 .status_reg = (void *)&PIK_SCP->PLL_STATUS0,
54 .lock_flag_mask = PLL_STATUS0_GPUPLLLOCK,
55 .initial_rate = 100 * FWK_MHZ,
56 .min_rate = MOD_SYSTEM_PLL_MIN_RATE,
57 .max_rate = MOD_SYSTEM_PLL_MAX_RATE,
58 .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL,
59 .defer_initialization = false,
60 }),
61 },
62 {
63 .name = "SWTCLKTCK_PLL",
64 .data = &((struct mod_system_pll_dev_config) {
65 .control_reg = (void *)SWCLKTCK_CONTROL,
66 .status_reg = NULL,
67 .initial_rate = 100 * FWK_MHZ,
68 .min_rate = MOD_SYSTEM_PLL_MIN_RATE,
69 .max_rate = MOD_SYSTEM_PLL_MAX_RATE,
70 .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL,
71 .defer_initialization = false,
72 }),
73 },
74 {
75 .name = "SYS_PLL",
76 .data = &((struct mod_system_pll_dev_config) {
77 .control_reg = (void *)PLL_SYSTEM,
78 .status_reg = (void *)&PIK_SCP->PLL_STATUS0,
79 .lock_flag_mask = PLL_STATUS0_SYSPLLLOCK,
80 .initial_rate = 2000 * FWK_MHZ,
81 .min_rate = MOD_SYSTEM_PLL_MIN_RATE,
82 .max_rate = MOD_SYSTEM_PLL_MAX_RATE,
83 .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL,
84 .defer_initialization = false,
85 }),
86 },
87 { 0 }, /* Termination description. */
88 };
89
system_pll_get_element_table(fwk_id_t module_id)90 static const struct fwk_element *system_pll_get_element_table
91 (fwk_id_t module_id)
92 {
93 return system_pll_element_table;
94 }
95
96 struct fwk_module_config config_system_pll = {
97 .elements = FWK_MODULE_DYNAMIC_ELEMENTS(system_pll_get_element_table),
98 };
99