1 /* 2 * Arm SCP/MCP Software 3 * Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef FMW_CMSIS_H 9 #define FMW_CMSIS_H 10 11 #include <stdint.h> 12 13 #define __CHECK_DEVICE_DEFINES 14 #define __CM3_REV 0x0201U 15 #define __MPU_PRESENT 1U 16 #define __NVIC_PRIO_BITS 3U 17 #define __Vendor_SysTickConfig 0U 18 #define __VTOR_PRESENT 1U 19 20 extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock)*/ 21 typedef enum IRQn { 22 Reset_IRQn = -15, 23 NonMaskableInt_IRQn = -14, 24 HardFault_IRQn = -13, 25 MemoryManagement_IRQn = -12, 26 BusFault_IRQn = -11, 27 UsageFault_IRQn = -10, 28 SVCall_IRQn = -5, 29 DebugMonitor_IRQn = -4, 30 PendSV_IRQn = -2, 31 SysTick_IRQn = -1, 32 33 TIM32KHZ_IRQ = 0, /* 32KHz Physical Timer */ 34 CDBG_PWR_UP_REQ_IRQ = 1, /* Coresight Debug Power Request */ 35 CSYS_PWR_UP_REQ_IRQ = 2, /* Coresight System Power Request */ 36 CDBG_RST_REQ_IRQ = 3, /* Coresight Debug Reset Request */ 37 RESERVED4_IRQ = 4, /* Reserved */ 38 RESERVED5_IRQ = 5, /* Reserved */ 39 RESERVED6_IRQ = 6, /* Reserved */ 40 RESERVED7_IRQ = 7, /* Reserved */ 41 RESERVED8_IRQ = 8, /* Reserved */ 42 RESERVED9_IRQ = 9, /* Reserved */ 43 RESERVED10_IRQ = 10, /* Reserved */ 44 RESERVED11_IRQ = 11, /* Reserved */ 45 RESERVED12_IRQ = 12, /* Reserved */ 46 RESERVED13_IRQ = 13, /* Reserved */ 47 RESERVED14_IRQ = 14, /* Reserved */ 48 RESERVED15_IRQ = 15, /* Reserved */ 49 SOC_WAKEUP0_IRQ = 16, /* SoC Expansion Wakeup */ 50 SOC_WAKEUP1_IRQ = 17, /* SoC Expansion Wakeup */ 51 SOC_WAKEUP2_IRQ = 18, /* SoC Expansion Wakeup */ 52 SOC_WAKEUP3_IRQ = 19, /* SoC Expansion Wakeup */ 53 SOC_WAKEUP4_IRQ = 20, /* SoC Expansion Wakeup */ 54 SOC_WAKEUP5_IRQ = 21, /* SoC Expansion Wakeup */ 55 SOC_WAKEUP6_IRQ = 22, /* SoC Expansion Wakeup */ 56 SOC_WAKEUP7_IRQ = 23, /* SoC Expansion Wakeup */ 57 SOC_WAKEUP8_IRQ = 24, /* SoC Expansion Wakeup */ 58 SOC_WAKEUP9_IRQ = 25, /* SoC Expansion Wakeup */ 59 SOC_WAKEUP10_IRQ = 26, /* SoC Expansion Wakeup */ 60 SOC_WAKEUP11_IRQ = 27, /* SoC Expansion Wakeup */ 61 SOC_WAKEUP12_IRQ = 28, /* SoC Expansion Wakeup */ 62 SOC_WAKEUP13_IRQ = 29, /* SoC Expansion Wakeup */ 63 SOC_WAKEUP14_IRQ = 30, /* SoC Expansion Wakeup */ 64 SOC_WAKEUP15_IRQ = 31, /* SoC Expansion Wakeup */ 65 PPU_SCP_IRQ = 32, /* SCP Power Policy Unit */ 66 TIMREFCLK_IRQ = 33, /* REFCLK Physical Timer */ 67 MHU_HIGH_PRIO_IRQ = 34, /* MHU High Priority */ 68 MHU_LOW_PRIO_IRQ = 35, /* MHU Low Priority */ 69 MHU_SECURE_IRQ = 36, /* MHU Secure */ 70 CTI_TRIGGER0_IRQ = 37, /* SCP CTI Trigger */ 71 CTI_TRIGGER1_IRQ = 38, /* SCP CTI Trigger */ 72 GIC_ERROR_ECC_IRQ = 39, /* GIC Error (ECC Fatal) */ 73 GIC_ERROR_AXIM_IRQ = 40, /* GIC Error (AXIM) */ 74 DMC_RESERVED0_IRQ = 41, /* DMC, Reserved */ 75 DMC_0_ERROR_ECC_IRQ = 42, /* DMC0 Combined ECC Error */ 76 DMC_0_ERROR_ACCESS_IRQ = 43, /* DMC0 Combined Misc Access Error */ 77 DMC_RESERVED1_IRQ = 44, /* DMC, Reserved */ 78 DMC_RESERVED2_IRQ = 45, /* DMC, Reserved */ 79 DMC_1_ERROR_ECC_IRQ = 46, /* DMC1 Combined ECC Error */ 80 DMC_1_ERROR_ACCESS_IRQ = 47, /* DMC1 Combined Misc Access Error */ 81 DMC_RESERVED3_IRQ = 48, /* DMC, Reserved */ 82 DMC_RESERVED4_IRQ = 49, /* DMC, Reserved */ 83 DMC_2_ERROR_ECC_IRQ = 50, /* DMC2 Combined ECC Error */ 84 DMC_2_ERROR_ACCESS_IRQ = 51, /* DMC2 Combined Misc Access Error */ 85 DMC_RESERVED5_IRQ = 52, /* DMC, Reserved */ 86 DMC_RESERVED6_IRQ = 53, /* DMC, Reserved */ 87 DMC_3_ERROR_ECC_IRQ = 54, /* DMC3 Combined ECC Error */ 88 DMC_3_ERROR_ACCESS_IRQ = 55, /* DMC3 Combined Misc Access Error */ 89 DMC_RESERVED7_IRQ = 56, /* DMC, Reserved */ 90 RESERVED57_IRQ = 57, /* Reserved */ 91 RESERVED58_IRQ = 58, /* Reserved */ 92 RESERVED59_IRQ = 59, /* Reserved */ 93 RESERVED60_IRQ = 60, /* Reserved */ 94 RESERVED61_IRQ = 61, /* Reserved */ 95 RESERVED62_IRQ = 62, /* Reserved */ 96 RESERVED63_IRQ = 63, /* Reserved */ 97 PPU_CLUS0CORE0_IRQ = 64, /* Cluster 0 Core 0 Power Policy Unit */ 98 PPU_CLUS0CORE1_IRQ = 65, /* Cluster 0 Core 1 Power Policy Unit */ 99 PPU_CLUS0CORE2_IRQ = 66, /* Cluster 0 Core 2 Power Policy Unit */ 100 PPU_CLUS0CORE3_IRQ = 67, /* Cluster 0 Core 3 Power Policy Unit */ 101 PPU_CLUS0_IRQ = 68, /* Cluster 0 Power Policy Unit */ 102 PPU_CLUS1CORE0_IRQ = 69, /* Cluster 1 Core 0 Power Policy Unit */ 103 PPU_CLUS1CORE1_IRQ = 70, /* Cluster 1 Core 1 Power Policy Unit */ 104 PPU_CLUS1CORE2_IRQ = 71, /* Cluster 1 Core 2 Power Policy Unit */ 105 PPU_CLUS1CORE3_IRQ = 72, /* Cluster 1 Core 3 Power Policy Unit */ 106 PPU_CLUS1_IRQ = 73, /* Cluster 1 Power Policy Unit */ 107 PPU_SYS0_IRQ = 74, /* System Power Policy Unit 0 */ 108 PPU_SYS1_IRQ = 75, /* System Power Policy Unit 1 */ 109 PPU_GPU_IRQ = 76, /* GPU Power Policy Unit */ 110 PPU_VPU_IRQ = 77, /* Video Power Policy Unit */ 111 PPU_DPU_IRQ = 78, /* Display Power Policy Unit 0 */ 112 RESERVED79_IRQ = 79, /* Reserved */ 113 RESERVED80_IRQ = 80, /* Reserved */ 114 PPU_DEBUG_IRQ = 81, /* DBGSYS Power Policy Unit */ 115 PPU_DEBUG_CHAIN_IRQ = 82, /* Debug chain Power Policy Unit */ 116 RESERVED83_IRQ = 83, /* Reserved */ 117 RESERVED84_IRQ = 84, /* Reserved */ 118 RESERVED85_IRQ = 85, /* Reserved */ 119 RESERVED86_IRQ = 86, /* Reserved */ 120 RESERVED87_IRQ = 87, /* Reserved */ 121 RESERVED88_IRQ = 88, /* Reserved */ 122 RESERVED89_IRQ = 89, /* Reserved */ 123 PPU_CLUS0CORE4_IRQ = 90, /* Cluster 0 Core 4 Power Policy Unit */ 124 PPU_CLUS0CORE5_IRQ = 91, /* Cluster 0 Core 5 Power Policy Unit */ 125 PPU_CLUS0CORE6_IRQ = 92, /* Cluster 0 Core 6 Power Policy Unit */ 126 PPU_CLUS0CORE7_IRQ = 93, /* Cluster 0 Core 7 Power Policy Unit */ 127 PPU_CLUS1CORE4_IRQ = 94, /* Cluster 1 Core 4 Power Policy Unit */ 128 PPU_CLUS1CORE5_IRQ = 95, /* Cluster 1 Core 5 Power Policy Unit */ 129 PPU_CLUS1CORE6_IRQ = 96, /* Cluster 1 Core 6 Power Policy Unit */ 130 PPU_CLUS1CORE7_IRQ = 97, /* Cluster 1 Core 7 Power Policy Unit */ 131 PLL_CLUS0_LOCK_IRQ = 98, /* Cluster 0 CPU PLL Lock */ 132 PLL_CLUS1_LOCK_IRQ = 99, /* Cluster 1 CPU PLL Lock */ 133 PLL_GPU_LOCK_IRQ = 100, /* GPU PLL Lock */ 134 PLL_VPU_LOCK_IRQ = 101, /* Video PLL Lock */ 135 PLL_SYS_LOCK_IRQ = 102, /* System PLL Lock */ 136 PLL_DPU_LOCK_IRQ = 103, /* Display PLL Lock */ 137 PLL_CLUS0CORE0_IRQ = 104, /* Cluster 0 PLL0 Lock */ 138 PLL_CLUS0CORE1_IRQ = 105, /* Cluster 0 PLL1 Lock */ 139 PLL_CLUS0CORE2_IRQ = 106, /* Cluster 0 PLL2 Lock */ 140 PLL_CLUS0CORE3_IRQ = 107, /* Cluster 0 PLL3 Lock */ 141 PLL_CLUS0CORE4_IRQ = 108, /* Cluster 0 PLL4 Lock */ 142 PLL_CLUS0CORE5_IRQ = 109, /* Cluster 0 PLL5 Lock */ 143 PLL_CLUS0CORE6_IRQ = 110, /* Cluster 0 PLL6 Lock */ 144 PLL_CLUS0CORE7_IRQ = 111, /* Cluster 0 PLL7 Lock */ 145 PLL_CLUS1CORE0_IRQ = 112, /* Cluster 1 PLL0 Lock */ 146 PLL_CLUS1CORE1_IRQ = 113, /* Cluster 1 PLL1 Lock */ 147 PLL_CLUS1CORE2_IRQ = 114, /* Cluster 1 PLL2 Lock */ 148 PLL_CLUS1CORE3_IRQ = 115, /* Cluster 1 PLL3 Lock */ 149 PLL_CLUS1CORE4_IRQ = 116, /* Cluster 1 PLL4 Lock */ 150 PLL_CLUS1CORE5_IRQ = 117, /* Cluster 1 PLL5 Lock */ 151 PLL_CLUS1CORE6_IRQ = 118, /* Cluster 1 PLL6 Lock */ 152 PLL_CLUS1CORE7_IRQ = 119, /* Cluster 1 PLL7 Lock */ 153 DBG_PWR_REQ0_IRQ = 120, /* Debug power request 0 */ 154 DBG_PWR_REQ1_IRQ = 121, /* Debug power request 1 */ 155 DBG_PWR_REQ2_IRQ = 122, /* Debug power request 2 */ 156 DBG_PWR_REQ3_IRQ = 123, /* Debug power request 3 */ 157 DBG_RST_REQ_IRQ = 124, /* Debug reset request */ 158 SYS_PWR_REQ0_IRQ = 125, /* System power request 0 */ 159 SYS_PWR_REQ1_IRQ = 126, /* System power request 1 */ 160 SYS_PWR_REQ2_IRQ = 127, /* System power request 2 */ 161 SYS_PWR_REQ3_IRQ = 128, /* System power request 3 */ 162 SYS_RST_REQ_IRQ = 129, /* System reset request */ 163 DBG_CHN_PWRUP_IRQ = 130, /* Debug chain power up */ 164 RESERVED131_IRQ = 131, /* Reserved */ 165 RESERVED132_IRQ = 132, /* Reserved */ 166 RESERVED133_IRQ = 133, /* Reserved */ 167 RESERVED134_IRQ = 134, /* Reserved */ 168 RESERVED135_IRQ = 135, /* Reserved */ 169 RESERVED136_IRQ = 136, /* Reserved */ 170 RESERVED137_IRQ = 137, /* Reserved */ 171 RESERVED138_IRQ = 138, /* Reserved */ 172 RESERVED139_IRQ = 139, /* Reserved */ 173 RESERVED140_IRQ = 140, /* Reserved */ 174 RESERVED141_IRQ = 141, /* Reserved */ 175 RESERVED142_IRQ = 142, /* Reserved */ 176 RESERVED143_IRQ = 143, /* Reserved */ 177 RESERVED144_IRQ = 144, /* Reserved */ 178 RESERVED145_IRQ = 145, /* Reserved */ 179 RESERVED146_IRQ = 146, /* Reserved */ 180 RESERVED147_IRQ = 147, /* Reserved */ 181 RESERVED148_IRQ = 148, /* Reserved */ 182 RESERVED149_IRQ = 149, /* Reserved */ 183 RESERVED150_IRQ = 150, /* Reserved */ 184 RESERVED151_IRQ = 151, /* Reserved */ 185 RESERVED152_IRQ = 152, /* Reserved */ 186 RESERVED153_IRQ = 153, /* Reserved */ 187 RESERVED154_IRQ = 154, /* Reserved */ 188 RESERVED155_IRQ = 155, /* Reserved */ 189 RESERVED156_IRQ = 156, /* Reserved */ 190 RESERVED157_IRQ = 157, /* Reserved */ 191 RESERVED158_IRQ = 158, /* Reserved */ 192 RESERVED159_IRQ = 159, /* Reserved */ 193 SCP_EXT_INTR0_IRQ = 160, /* SCP Customer Extension */ 194 SCP_EXT_INTR1_IRQ = 161, /* SCP Customer Extension */ 195 SCP_EXT_INTR2_IRQ = 162, /* SCP Customer Extension */ 196 SCP_EXT_INTR3_IRQ = 163, /* SCP Customer Extension */ 197 SCP_EXT_INTR4_IRQ = 164, /* SCP Customer Extension */ 198 SCP_EXT_INTR5_IRQ = 165, /* SCP Customer Extension */ 199 SCP_EXT_INTR6_IRQ = 166, /* SCP Customer Extension */ 200 SCP_EXT_INTR7_IRQ = 167, /* SCP Customer Extension */ 201 SCP_EXT_INTR8_IRQ = 168, /* SCP Customer Extension */ 202 SCP_EXT_INTR9_IRQ = 169, /* SCP Customer Extension */ 203 SCP_EXT_INTR10_IRQ = 170, /* SCP Customer Extension */ 204 SCP_EXT_INTR11_IRQ = 171, /* SCP Customer Extension */ 205 SCP_EXT_INTR12_IRQ = 172, /* SCP Customer Extension */ 206 SCP_EXT_INTR13_IRQ = 173, /* SCP Customer Extension */ 207 SCP_EXT_INTR14_IRQ = 174, /* SCP Customer Extension */ 208 SCP_EXT_INTR15_IRQ = 175, /* SCP Customer Extension */ 209 SCP_EXT_INTR16_IRQ = 176, /* SCP Customer Extension */ 210 SCP_EXT_INTR17_IRQ = 177, /* SCP Customer Extension */ 211 SCP_EXT_INTR18_IRQ = 178, /* SCP Customer Extension */ 212 SCP_EXT_INTR19_IRQ = 179, /* SCP Customer Extension */ 213 SCP_EXT_INTR20_IRQ = 180, /* SCP Customer Extension */ 214 SCP_EXT_INTR21_IRQ = 181, /* SCP Customer Extension */ 215 SCP_EXT_INTR22_IRQ = 182, /* SCP Customer Extension */ 216 SCP_EXT_INTR23_IRQ = 183, /* SCP Customer Extension */ 217 SCP_EXT_INTR24_IRQ = 184, /* SCP Customer Extension */ 218 SCP_EXT_INTR25_IRQ = 185, /* SCP Customer Extension */ 219 SCP_EXT_INTR26_IRQ = 186, /* SCP Customer Extension */ 220 SCP_EXT_INTR27_IRQ = 187, /* SCP Customer Extension */ 221 SCP_EXT_INTR28_IRQ = 188, /* SCP Customer Extension */ 222 SCP_EXT_INTR29_IRQ = 189, /* SCP Customer Extension */ 223 SCP_EXT_INTR30_IRQ = 190, /* SCP Customer Extension */ 224 SCP_EXT_INTR31_IRQ = 191, /* SCP Customer Extension */ 225 226 IRQn_MAX = INT16_MAX, 227 } IRQn_Type; 228 229 #include <core_cm3.h> 230 231 #endif /* FMW_CMSIS_H */ 232