1 /* 2 * Arm SCP/MCP Software 3 * Copyright (c) 2017-2021, Arm Limited and Contributors. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef SGM776_MMAP_H 9 #define SGM776_MMAP_H 10 11 #include <stdint.h> 12 13 /* 14 * Top-level base addresses 15 */ 16 #define EXPANSION0_BASE UINT32_C(0x40000000) 17 #define PERIPHERAL_BASE UINT32_C(0x44000000) 18 #define POWER_PERIPHERAL_BASE UINT32_C(0x50000000) 19 #define SYS0_BASE UINT32_C(0x60000000) 20 #define SYS1_BASE UINT32_C(0xA0000000) 21 #define PPB_INTERNAL_BASE UINT32_C(0xE0000000) 22 #define PPB_EXTERNAL_BASE UINT32_C(0xE0040000) 23 #define EXPANSION1_BASE UINT32_C(0xE0100000) 24 25 /* 26 * Peripherals 27 */ 28 #define REFCLK_CNTCTL_BASE (PERIPHERAL_BASE + 0x0000) 29 #define REFCLK_CNTBASE0_BASE (PERIPHERAL_BASE + 0x1000) 30 #define MHU_RECV_NS_BASE (PERIPHERAL_BASE + 0x2000) 31 #define MHU_SEND_NS_BASE (PERIPHERAL_BASE + 0x3000) 32 #define MHU_RECV_S_BASE (PERIPHERAL_BASE + 0x4000) 33 #define MHU_SEND_S_BASE (PERIPHERAL_BASE + 0x5000) 34 #define WDOG_BASE (PERIPHERAL_BASE + 0x6000) 35 #define S32K_CNTCONTROL_BASE (PERIPHERAL_BASE + 0x7000) 36 #define S32K_CNTCTL_BASE (PERIPHERAL_BASE + 0x8000) 37 #define S32K_CNTBASE0_BASE (PERIPHERAL_BASE + 0x9000) 38 #define CS_CNTCONTROL_BASE (PERIPHERAL_BASE + 0xA000) 39 40 /* 41 * Power control peripherals 42 */ 43 #define PIK_SCP_BASE (POWER_PERIPHERAL_BASE + 0x000000) 44 #define PIK_DEBUG_BASE (POWER_PERIPHERAL_BASE + 0x020000) 45 #define SENSOR_DEBUG_BASE (POWER_PERIPHERAL_BASE + 0x030000) 46 #define PIK_SYSTEM_BASE (POWER_PERIPHERAL_BASE + 0x040000) 47 #define SENSOR_SYSTEM_BASE (POWER_PERIPHERAL_BASE + 0x050000) 48 #define PIK_CLUS0_BASE (POWER_PERIPHERAL_BASE + 0x060000) 49 #define SENSOR_CLUS0_BASE (POWER_PERIPHERAL_BASE + 0x070000) 50 #define PIK_CLUS1_BASE (POWER_PERIPHERAL_BASE + 0x080000) 51 #define SENSOR_CLUS1_BASE (POWER_PERIPHERAL_BASE + 0x090000) 52 #define PIK_GPU_BASE (POWER_PERIPHERAL_BASE + 0x0A0000) 53 #define SENSOR_GPU_BASE (POWER_PERIPHERAL_BASE + 0x0B0000) 54 #define PIK_VPU_BASE (POWER_PERIPHERAL_BASE + 0x0C0000) 55 #define SENSOR_VPU_BASE (POWER_PERIPHERAL_BASE + 0x0D0000) 56 #define PIK_DPU_BASE (POWER_PERIPHERAL_BASE + 0x0E0000) 57 #define SENSOR_DPU_BASE (POWER_PERIPHERAL_BASE + 0x0F0000) 58 #define PIK_DEBUG_CHAIN_BASE (POWER_PERIPHERAL_BASE + 0x100000) 59 60 /* 61 * PPU base address 62 */ 63 #define PPU_SCP_BASE (PIK_SCP_BASE + 0x1000) 64 #define PPU_SYS0_BASE (PIK_SYSTEM_BASE + 0x1000) 65 #define PPU_SYS1_BASE (PIK_SYSTEM_BASE + 0x2000) 66 #define PPU_DEBUG_BASE (PIK_DEBUG_BASE + 0x1000) 67 #define PPU_CLUS0CORE0_BASE (PIK_CLUS0_BASE + 0x2000) 68 #define PPU_CLUS0CORE1_BASE (PIK_CLUS0_BASE + 0x3000) 69 #define PPU_CLUS0CORE2_BASE (PIK_CLUS0_BASE + 0x4000) 70 #define PPU_CLUS0CORE3_BASE (PIK_CLUS0_BASE + 0x5000) 71 #define PPU_CLUS0CORE4_BASE (PIK_CLUS0_BASE + 0x6000) 72 #define PPU_CLUS0CORE5_BASE (PIK_CLUS0_BASE + 0x7000) 73 #define PPU_CLUS0CORE6_BASE (PIK_CLUS0_BASE + 0x8000) 74 #define PPU_CLUS0CORE7_BASE (PIK_CLUS0_BASE + 0x9000) 75 #define PPU_CLUS0_BASE (PIK_CLUS0_BASE + 0x1000) 76 #define PPU_CLUS1CORE0_BASE (PIK_CLUS1_BASE + 0x2000) 77 #define PPU_CLUS1CORE1_BASE (PIK_CLUS1_BASE + 0x3000) 78 #define PPU_CLUS1CORE2_BASE (PIK_CLUS1_BASE + 0x4000) 79 #define PPU_CLUS1CORE3_BASE (PIK_CLUS1_BASE + 0x5000) 80 #define PPU_CLUS1_BASE (PIK_CLUS1_BASE + 0x1000) 81 #define PPU_GPU_BASE (PIK_GPU_BASE + 0x1000) 82 #define PPU_VPU_BASE (PIK_VPU_BASE + 0x1000) 83 #define PPU_DPU_BASE (PIK_DPU_BASE + 0x1000) 84 85 /* 86 * System access port 1 87 */ 88 #define TRUSTED_RAM_BASE (SYS1_BASE + 0x04000000) 89 #define NONTRUSTED_RAM_BASE (SYS1_BASE + 0x06000000) 90 #define CCI_BASE (SYS1_BASE + 0x2A000000) 91 #define ARACHNE_BASE (SYS1_BASE + 0x2A100000) 92 #define SID_BASE (SYS1_BASE + 0x2A420000) 93 #define REFCLK_CNTCONTROL_BASE (SYS1_BASE + 0x2A430000) 94 #define DMC_BASE (SYS1_BASE + 0x2A500000) 95 96 #endif /* SGM776_MMAP_H */ 97