1 /* 2 * Arm SCP/MCP Software 3 * Copyright (c) 2017-2021, Arm Limited and Contributors. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef SGM776_PIK_GPU_H 9 #define SGM776_PIK_GPU_H 10 11 #include <fwk_macros.h> 12 13 #include <stdint.h> 14 15 /*! 16 * \brief GPU PIK register definitions 17 */ 18 struct pik_gpu_reg { 19 uint8_t RESERVED0[0x810]; 20 FWK_RW uint32_t GPUCLK_CTRL; 21 FWK_RW uint32_t GPUCLK_DIV1; 22 FWK_RW uint32_t GPUCLK_DIV2; 23 uint8_t RESERVED1[0x820 - 0x81C]; 24 FWK_RW uint32_t ACLKGPU_CTRL; 25 uint8_t RESERVED2[0xA00 - 0x824]; 26 FWK_R uint32_t CLKFORCE_STATUS; 27 FWK_W uint32_t CLKFORCE_SET; 28 FWK_W uint32_t CLKFORCE_CLR; 29 uint8_t RESERVED3[0xFBC - 0xA0C]; 30 FWK_R uint32_t CAP; 31 FWK_R uint32_t PCL_CONFIG; 32 uint8_t RESERVED4[0xFD0 - 0xFC4]; 33 FWK_R uint32_t PID4; 34 FWK_R uint32_t PID5; 35 FWK_R uint32_t PID6; 36 FWK_R uint32_t PID7; 37 FWK_R uint32_t PID0; 38 FWK_R uint32_t PID1; 39 FWK_R uint32_t PID2; 40 FWK_R uint32_t PID3; 41 FWK_R uint32_t ID0; 42 FWK_R uint32_t ID1; 43 FWK_R uint32_t ID2; 44 FWK_R uint32_t ID3; 45 }; 46 #endif /* SGM776_PIK_GPU_H */ 47