1 /* 2 * Arm SCP/MCP Software 3 * Copyright (c) 2017-2021, Arm Limited and Contributors. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef SGM776_PIK_SCP_H 9 #define SGM776_PIK_SCP_H 10 11 #include <fwk_macros.h> 12 13 #include <stdint.h> 14 15 /*! 16 * \brief SCP PIK register definitions 17 */ 18 struct pik_scp_reg { 19 uint8_t RESERVED0[0x10]; 20 FWK_RW uint32_t RESET_SYNDROME; 21 FWK_RW uint32_t WIC_CTRL; 22 FWK_R uint32_t WIC_STATUS; 23 uint8_t RESERVED1[0xA00 - 0x1C]; 24 FWK_R uint32_t CLKFORCE_STATUS; 25 FWK_RW uint32_t CLKFORCE_SET; 26 FWK_RW uint32_t CLKFORCE_CLR; 27 uint32_t RESERVED2; 28 FWK_R uint32_t PLL_STATUS0; 29 FWK_R uint32_t PLL_STATUS1; 30 uint8_t RESERVED3[0xFC0 - 0xA18]; 31 FWK_R uint32_t PCL_CONFIG; 32 uint8_t RESERVED4[0xFD0 - 0xFC4]; 33 FWK_R uint32_t PID4; 34 FWK_R uint32_t PID5; 35 FWK_R uint32_t PID6; 36 FWK_R uint32_t PID7; 37 FWK_R uint32_t PID0; 38 FWK_R uint32_t PID1; 39 FWK_R uint32_t PID2; 40 FWK_R uint32_t PID3; 41 FWK_R uint32_t ID0; 42 FWK_R uint32_t ID1; 43 FWK_R uint32_t ID2; 44 FWK_R uint32_t ID3; 45 }; 46 47 #define PLL_STATUS0_REFCLK UINT32_C(0x00000001) 48 #define PLL_STATUS0_GPUPLLLOCK UINT32_C(0x00000008) 49 #define PLL_STATUS0_VIDEOPLLLOCK UINT32_C(0x00000010) 50 #define PLL_STATUS0_SYSPLLLOCK UINT32_C(0x00000020) 51 #define PLL_STATUS0_DISPLAYPLLLOCK UINT32_C(0x00000040) 52 53 #define PLL_STATUS1_CPUPLLLOCK(CORE, PLL) \ 54 ((uint32_t)((1 << (PLL)) << ((CORE) * 8))) 55 56 #define RESET_SYNDROME_PORESET UINT32_C(0x01) 57 #define RESET_SYNDROME_WDOGRESET_SCP UINT32_C(0x02) 58 #define RESET_SYNDROME_WDOGRESET_SYS UINT32_C(0x04) 59 #define RESET_SYNDROME_SYSRESETREQ UINT32_C(0x08) 60 #define RESET_SYNDROME_SCPM3LOCKUP UINT32_C(0x10) 61 62 #endif /* SGM776_PIK_SCP_H */ 63