1 /* 2 * Arm SCP/MCP Software 3 * Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef MMU500_H 9 #define MMU500_H 10 11 #include <fwk_macros.h> 12 13 #include <stdint.h> 14 15 #define SMMU_NUMSMRG 16 16 #define SMMU_NUMCB 8 17 18 typedef struct { 19 FWK_RW uint32_t CR0; 20 FWK_RW uint32_t SCR1; 21 uint32_t reserved0[(0x010 - 0x008) / 4]; 22 FWK_RW uint32_t ACR; 23 uint32_t reserved1[(0x020 - 0x014) / 4]; 24 FWK_R uint32_t IDR0; 25 FWK_R uint32_t IDR1; 26 FWK_R uint32_t IDR2; 27 uint32_t reserved2[(0x03C - 0x02C) / 4]; 28 FWK_R uint32_t IDR7; 29 FWK_RW uint32_t GFAR_L; 30 FWK_RW uint32_t GFAR_U; 31 FWK_RW uint32_t GFSR; 32 FWK_W uint32_t GFSRRESTORE; 33 FWK_RW uint32_t GFSYNR0; 34 FWK_RW uint32_t GFSYNR1; 35 uint32_t reserved3[(0x060 - 0x058) / 4]; 36 FWK_W uint32_t STLBIALL; 37 FWK_W uint32_t TLBIVMID; 38 FWK_W uint32_t TLBIALLNSNH; 39 uint32_t reserved5; 40 FWK_W uint32_t TLBGSYNC; 41 FWK_R uint32_t TLBGSTATUS; 42 uint32_t reserved6[(0x080 - 0x078) / 4]; 43 FWK_RW uint32_t DBGRPTR; 44 FWK_R uint32_t DBGRDATA; 45 uint32_t reserved7[(0x800 - 0x088) / 4]; 46 FWK_RW uint32_t SMR[SMMU_NUMSMRG]; 47 uint32_t reserved8[(0xC00 - (0x800 + SMMU_NUMSMRG * 4)) / 4]; 48 FWK_RW uint32_t S2CR[SMMU_NUMSMRG]; 49 uint32_t reserved9[(0x1000 - (0xC00 + SMMU_NUMSMRG * 4)) / 4]; 50 } GSPACE0_Type_t; 51 52 typedef struct { 53 FWK_RW uint32_t CBAR[SMMU_NUMCB]; 54 uint32_t reserved0[(0x400 - (0x000 + SMMU_NUMCB * 4)) / 4]; 55 FWK_RW uint32_t CBFRSYNRA[SMMU_NUMCB]; 56 uint32_t reserved1[(0x800 - (0x400 + SMMU_NUMCB * 4)) / 4]; 57 FWK_RW uint32_t CBA2R[SMMU_NUMCB]; 58 uint32_t reserved2[(0x1000 - (0x800 + SMMU_NUMCB * 4)) / 4]; 59 } GSPACE1_Type_t; 60 61 typedef struct { 62 FWK_RW uint32_t CB_SCTLR; 63 FWK_RW uint32_t CB_ACTLR; 64 FWK_W uint32_t CB_RESUME; 65 uint32_t reserved0; 66 FWK_RW uint32_t CB_TCR2; 67 uint32_t reserved1[(0x20 - 0x14) / 4]; 68 FWK_RW uint64_t CB_TTBR0; 69 FWK_RW uint64_t CB_TTBR1; 70 FWK_RW uint32_t CB_TCR; 71 FWK_RW uint32_t CB_CONTEXTIDR; 72 FWK_RW uint32_t CB_MAIR0; 73 FWK_RW uint32_t CB_MAIR1; 74 uint32_t reserved2[(0x50 - 0x40) / 4]; 75 FWK_RW uint64_t CB_PAR; 76 FWK_RW uint32_t CB_FSR; 77 FWK_W uint32_t CB_FSRRESTORE; 78 FWK_RW uint64_t CB_FAR; 79 FWK_RW uint32_t CB_FSYNC0; 80 FWK_RW uint32_t CB_FSYNC1; 81 uint32_t reserved3[(0x1000 - 0x70) / 4]; 82 } TCB_Type_t; 83 84 typedef struct { 85 GSPACE0_Type_t GR0; 86 GSPACE1_Type_t GR1; 87 uint32_t reserved2[(0x3000 - 0x2000) / 4]; 88 uint32_t reserved3[(0x4000 - 0x3000) / 4]; 89 FWK_RW uint32_t SSDR[256]; 90 uint32_t reserved4[(0x8000 - 0x4400) / 4]; 91 TCB_Type_t TCB[SMMU_NUMCB]; 92 } MMU500_Type_t; 93 94 typedef struct { 95 unsigned stream_match_mask : 15; 96 unsigned stream_match_id : 15; 97 uint64_t base_addr; 98 } MMU500_ContextInfo_t; 99 100 //#define SMMU_BASE 0x50240000 //mmu_a2p 101 //#define SMMU_BASE 0x50250000 //mmu_p2a 102 //#define SMMU_BASE 0xd1e00000 //mmu_scb 103 //#define SMMU ((MMU500_Type_t *) SMMU_BASE) 104 105 /* --------------------------------- */ 106 /* ---- Global Space Register 0 ---- */ 107 108 #define SMMU_ACR_PAGESIZE_64K ((uint32_t)0x1 << 16) 109 #define SMMU_ACR_S2CRB_TLBEN ((uint32_t)0x1 << 10) 110 #define SMMU_ACR_MMUDISB_TLBEN ((uint32_t)0x1 << 9) 111 #define SMMU_ACR_SMTNMB_TLBEN ((uint32_t)0x1 << 8) 112 113 #define SMMU_IDR0_NUMSMRG ((uint32_t)0xff << 0) 114 115 #define SMMU_IDR1_NUMCB ((uint32_t)0xff << 0) 116 #define SMMU_IDR1_PAGESIZE ((uint32_t)1U << 31) 117 118 #define SMMU_CR0_SMCFCFG ((uint32_t)1 << 21) 119 #define SMMU_CR0_USFCFG ((uint32_t)1 << 10) 120 #define SMMU_CR0_GSE ((uint32_t)1 << 9) 121 #define SMMU_CR0_STALLD ((uint32_t)1 << 8) 122 #define SMMU_CR0_GCFGFIE ((uint32_t)1 << 5) 123 #define SMMU_CR0_GCFGFRE ((uint32_t)1 << 4) 124 // 125 #define SMMU_CR0_GFIE ((uint32_t)1 << 2) 126 #define SMMU_CR0_GFRE ((uint32_t)1 << 1) 127 #define SMMU_CR0_CLIENTPD ((uint32_t)1 << 0) 128 129 #define SMMU_SCR1_NSNUMCBO ((uint32_t)0xff << 0) 130 #define SMMU_SCR1_NSNUMSMRGO ((uint32_t)0xff << 8) 131 #define SMMU_SCR1_NSNUMCBO_OFFSET ((uint32_t)0) 132 #define SMMU_SCR1_NSNUMSMRGO_OFFSET ((uint32_t)8) 133 #define SMMU_SCR1_SPMEN ((uint32_t)1 << 27) 134 135 #define SMMU_TLBGSTATUS_GACTIVE ((uint32_t)1) 136 137 #define SMMU_SMRn_VALID ((uint32_t)1 << 31) 138 #define SMMU_SMRn_ID_OFFSET 0 139 140 #define SMMU_S2CRn_TYPE_CONTEXT ((uint32_t)0 << 16) 141 #define SMMU_S2CRn_TYPE_BYPASS ((uint32_t)1 << 16) 142 #define SMMU_S2CRn_TYPE_FAULT ((uint32_t)2 << 16) 143 144 #define SMMU_S2CRn_SH_DEF ((uint32_t)0 << 8) 145 #define SMMU_S2CRn_SH_OUTER ((uint32_t)1 << 8) 146 #define SMMU_S2CRn_SH_INNER ((uint32_t)2 << 8) 147 #define SMMU_S2CRn_SH_NON ((uint32_t)3 << 8) 148 149 #define SMMU_S2CRn_CBNDX_OFFSET 0 150 151 /* ---- Global Space Register 1 ---- */ 152 /* --------------------------------- */ 153 #define SMMU_CBAR_TYPE_STAGE2 ((uint32_t)0 << 16) 154 #define SMMU_CBAR_TYPE_STAGE1 ((uint32_t)1 << 16) 155 #define SMMU_CBAR_TYPE_STAGE1_2 ((uint32_t)3 << 16) 156 #define SMMU_CBAR_MEM_NORMAL ((uint32_t)0xf << 12) 157 158 #define SMMU_CBAR_HYPC ((uint32_t)1 << 10) 159 160 /* ------------------------------ */ 161 #define SMMU_CBA2R_MONC ((uint32_t)1 << 1) 162 #define SMMU_CBA2R_VA64 ((uint32_t)1 << 0) 163 164 /* ---- Translation Context Bank --- */ 165 /* ---- SCTLR ---------------------- */ 166 #define SMMU_SCTLR_SH_OUTER ((uint32_t)0x1 << 22) 167 #define SMMU_SCTLR_MEM_NORMAL ((uint32_t)0xf << 16) 168 #define SMMU_SCTLR_UWXN ((uint32_t)1 << 10) 169 #define SMMU_SCTLR_WXN ((uint32_t)1 << 9) 170 #define SMMU_SCTLR_HUPCF ((uint32_t)1 << 8) // Hit Under Previous Context Faut 171 #define SMMU_SCTLR_CFCFG ((uint32_t)1 << 7) // Context fault Configuration 172 #define SMMU_SCTLR_CFIE ((uint32_t)1 << 6) // Context Fault Interrupt Enable 173 #define SMMU_SCTLR_CFRE ((uint32_t)1 << 5) // Context Fault Report Enable 174 #define SMMU_SCTLR_E ((uint32_t)1 << 4) 175 #define SMMU_SCTLR_A ((uint32_t)1 << 3) 176 #define SMMU_SCTLR_AFE ((uint32_t)1 << 2) 177 #define SMMU_SCTLR_TRE ((uint32_t)1 << 1) 178 #define SMMU_SCTLR_M ((uint32_t)1 << 0) 179 180 /* ------- TCR ----------------- */ 181 #define SMMU_TCR_EPD1 ((uint32_t)1 << 23) 182 #define SMMU_TCR_A1 ((uint32_t)1 << 22) 183 184 #define SMMU_TCR_TG0_4KB ((uint32_t)0 << 14) 185 #define SMMU_TCR_TG0_16KB ((uint32_t)2 << 14) 186 #define SMMU_TCR_TG0_64KB ((uint32_t)1 << 14) 187 188 #define SMMU_TCR_SH0_NON ((uint32_t)0 << 12) 189 #define SMMU_TCR_SH0_RESERVED ((uint32_t)1 << 12) 190 #define SMMU_TCR_SH0_OUTER ((uint32_t)2 << 12) 191 #define SMMU_TCR_SH0_INNERN ((uint32_t)3 << 12) 192 193 #define SMMU_TCR_ORGN0_WBWA ((uint32_t)1 << 10) 194 #define SMMU_TCR_IRGN0_WBWA ((uint32_t)1 << 8) 195 196 #define SMMU_TCR_EPD0 ((uint32_t)1 << 7) 197 198 #define SMMU_TCR_T0SZ_4GB ((uint32_t)32 << 0) 199 #define SMMU_TCR_T0SZ_8GB ((uint32_t)31 << 0) 200 #define SMMU_TCR_T0SZ_16GB ((uint32_t)30 << 0) 201 #define SMMU_TCR_T0SZ_32GB ((uint32_t)29 << 0) 202 #define SMMU_TCR_T0SZ_64GB ((uint32_t)28 << 0) 203 #define SMMU_TCR_T0SZ_128GB ((uint32_t)27 << 0) 204 #define SMMU_TCR_T0SZ_256GB ((uint32_t)26 << 0) 205 #define SMMU_TCR_T0SZ_512GB ((uint32_t)25 << 0) 206 #define SMMU_TCR_T0SZ_1TB ((uint32_t)24 << 0) 207 #define SMMU_TCR_T0SZ_256TB ((uint32_t)16 << 0) 208 209 /* for stage2 */ 210 #define SMMU_TCR_PASIZE_4GB ((uint32_t)0 << 16) 211 #define SMMU_TCR_PASIZE_64GB ((uint32_t)1 << 16) 212 #define SMMU_TCR_PASIZE_1TB ((uint32_t)2 << 16) 213 214 #define SMMU_TCR_SL0_LV3 ((uint32_t)0 << 6) 215 #define SMMU_TCR_SL0_LV2 ((uint32_t)1 << 6) 216 #define SMMU_TCR_SL0_LV1 ((uint32_t)2 << 6) 217 218 /* ------- TCR2 ----------------- */ 219 #define SMMU_TCR2_SEP_41 ((uint32_t)3 << 15) 220 #define SMMU_TCR2_SEP_47 ((uint32_t)5 << 15) 221 #define SMMU_TCR2_PASIZE_32 ((uint32_t)0 << 0) 222 #define SMMU_TCR2_PASIZE_36 ((uint32_t)1 << 0) 223 #define SMMU_TCR2_PASIZE_40 ((uint32_t)2 << 0) 224 #define SMMU_TCR2_PASIZE_48 ((uint32_t)5 << 0) 225 226 /* ------------------------------ */ 227 228 #define SMMU_TTBRn_ADDR_MASK_1TB_64KB ((uint64_t)0x0000ffffe0000000) 229 #define SMMU_TTBRn_ASID_OFFSET 48 230 231 #define SMMU_TBUID_GPU ((uint32_t)0 << 10) 232 #define SMMU_TBUID_ETR ((uint32_t)1 << 10) 233 #define SMMU_TBUID_SCP ((uint32_t)2 << 10) 234 235 #ifdef __cplusplus 236 extern "C" { 237 #endif 238 /** 239 * MMU500 page table manipulators 240 */ 241 enum mmu500_granule { 242 MMU500_GRANULE_4KB = 0, 243 MMU500_GRANULE_16KB = 1, 244 MMU500_GRANULE_64KB = 2 245 }; 246 247 int32_t SMMU_s_init( 248 MMU500_Type_t *SMMU, 249 uint32_t num_context, 250 const MMU500_ContextInfo_t *context_info, 251 enum mmu500_granule granule); 252 int32_t SMMU_ns_init(MMU500_Type_t *SMMU, uint64_t addr); 253 void SMMU_ns_cb0_stage2_init(MMU500_Type_t *SMMU, uint64_t addr); 254 void SMMU_ns_cb0_stage1_init(MMU500_Type_t *SMMU, uint64_t addr); 255 void SMMU_ns_cb_stage1_init( 256 MMU500_Type_t *SMMU, 257 uint32_t cb, 258 uint64_t addr, 259 enum mmu500_granule granule); 260 void SMMU_s_disable(MMU500_Type_t *SMMU, uint32_t num_context); 261 262 #ifdef __cplusplus 263 } 264 #endif 265 266 #endif /* MMU500_H */ 267