1 /* 2 * Arm SCP/MCP Software 3 * Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef PIK_SYSTEM_H 9 #define PIK_SYSTEM_H 10 11 #include <fwk_macros.h> 12 13 #include <stdint.h> 14 15 typedef struct { 16 FWK_R uint32_t RESERVED0[512]; 17 FWK_RW uint32_t PPUCLK_CTRL; 18 FWK_RW uint32_t PPUCLK_DIV1; 19 FWK_R uint32_t RESERVED1[6]; 20 FWK_RW uint32_t CCNCLK_CTRL; 21 FWK_RW uint32_t CCNCLK_DIV1; 22 FWK_R uint32_t RESERVED2[10]; 23 FWK_RW uint32_t GICCLK_CTRL; 24 FWK_RW uint32_t GICCLK_DIV1; 25 FWK_R uint32_t RESERVED3[2]; 26 FWK_RW uint32_t PCLKSCP_CTRL; 27 FWK_RW uint32_t PCLKSCP_DIV1; 28 FWK_R uint32_t RESERVED4[2]; 29 FWK_RW uint32_t SYSPERCLK_CTRL; 30 FWK_RW uint32_t SYSPERCLK_DIV1; 31 FWK_R uint32_t RESERVED5[2]; 32 FWK_RW uint32_t DMCCLK_CTRL; 33 FWK_RW uint32_t DMCCLK_DIV1; 34 FWK_R uint32_t RESERVED6[2]; 35 FWK_RW uint32_t SYSPCLKDBG_CTRL; 36 FWK_RW uint32_t SYSPCLKDBG_DIV1; 37 FWK_R uint32_t RESERVED7[2]; 38 FWK_RW uint32_t UARTCLK_CTRL; 39 FWK_RW uint32_t UARTCLK_DIV1; 40 FWK_R uint32_t RESERVED8[86]; 41 FWK_R uint32_t CLKFORCE_STATUS; 42 FWK_RW uint32_t CLKFORCE_SET; 43 FWK_RW uint32_t CLKFORCE_CLR; 44 FWK_R uint32_t RESERVED9[63]; 45 FWK_RW uint32_t DMC_CONTROL; 46 FWK_RW uint32_t SYSTOP_RST_DLY; 47 FWK_R uint32_t RESERVED10[300]; 48 FWK_R uint32_t PIK_CONFIG; 49 FWK_R uint32_t RESERVED11[3]; 50 FWK_R uint32_t PID4; 51 FWK_R uint32_t PID5; 52 FWK_R uint32_t PID6; 53 FWK_R uint32_t PID7; 54 FWK_R uint32_t PID0; 55 FWK_R uint32_t PID1; 56 FWK_R uint32_t PID2; 57 FWK_R uint32_t PID3; 58 FWK_R uint32_t ID0; 59 FWK_R uint32_t ID1; 60 FWK_R uint32_t ID2; 61 FWK_R uint32_t ID3; 62 } pik_system_reg_t; 63 64 #endif /* PIK_SYSTEM_H */ 65