1 /*
2  * Arm SCP/MCP Software
3  * Copyright (c) 2015-2021, Arm Limited and Contributors. All rights reserved.
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 
8 #ifndef PPU_V0_H
9 #define PPU_V0_H
10 
11 /*!
12  * \cond
13  */
14 
15 #include <fwk_macros.h>
16 
17 #include <stdbool.h>
18 #include <stdint.h>
19 
20 struct ppu_v0_reg {
21     FWK_RW uint32_t POWER_POLICY;
22     FWK_R uint32_t POWER_STATUS;
23     FWK_R uint32_t STATIC_CFG_STATUS;
24     FWK_R uint32_t DEV_IF_IP_CUR_STATUS;
25     FWK_R uint32_t MISC_IP_CUR_STATUS;
26     FWK_R uint32_t STORED_STATUS;
27     FWK_W uint32_t OFF_MEM_RET_UNLOCK;
28     uint32_t RESERVED0;
29     FWK_RW uint32_t POWER_CFG;
30     uint32_t RESERVED1[3];
31     FWK_RW uint32_t IMR;
32     FWK_RW uint32_t ISR;
33     FWK_RW uint32_t IESR;
34     uint32_t RESERVED2[5];
35     FWK_RW uint32_t FUNC_RET_RAM_CFG;
36     FWK_RW uint32_t FULL_RET_RAM_CFG;
37     FWK_RW uint32_t MEM_RET_RAM_CFG;
38     uint32_t RESERVED3;
39     FWK_RW uint32_t MODE_ENTRY_DELAY_TIME_0;
40     FWK_RW uint32_t MODE_ENTRY_DELAY_TIME_1;
41     uint32_t RESERVED4[2];
42     FWK_RW uint32_t DEV_CONTROL_DELAY_CFG_0;
43     FWK_RW uint32_t DEV_CONTROL_DELAY_CFG_1;
44     uint8_t RESERVED5[0xFC8 - 0x78];
45     FWK_R uint32_t IMPLEMENTATION_ID;
46     FWK_R uint32_t ARCHITECTURE_ID;
47     FWK_R uint32_t PID4;
48     FWK_R uint32_t PID5;
49     FWK_R uint32_t PID6;
50     FWK_R uint32_t PID7;
51     FWK_R uint32_t PID0;
52     FWK_R uint32_t PID1;
53     FWK_R uint32_t PID2;
54     FWK_R uint32_t PID3;
55     FWK_R uint32_t CID0;
56     FWK_R uint32_t CID1;
57     FWK_R uint32_t CID2;
58     FWK_R uint32_t CID3;
59 };
60 
61 enum ppu_v0_mode {
62     PPU_V0_MODE_OFF = 0,
63     PPU_V0_MODE_MEM_RET = 1,
64     PPU_V0_MODE_LOGIC_RET = 2,
65     PPU_V0_MODE_FULL_RET = 3,
66     PPU_V0_MODE_MEM_OFF = 4,
67     PPU_V0_MODE_FUNC_RET = 5,
68     PPU_V0_MODE_ON = 6,
69     PPU_V0_MODE_WARM_RESET = 7,
70     PPU_V0_MODE_COUNT,
71 };
72 
73 /*
74  * Bit definitions for PPR
75  */
76 #define PPU_V0_PPR_POLICY UINT32_C(0x00000007)
77 #define PPU_V0_PPR_DYNAMIC_EN UINT32_C(0x00000100)
78 #define PPU_V0_PPR_EMULATED_EN UINT32_C(0x00000200)
79 #define PPU_V0_PPR_OFF_LOCK_EN UINT32_C(0x00001000)
80 
81 /*
82  * Bit definitions for PSR
83  */
84 #define PPU_V0_PSR_EMULATED UINT32_C(0x00000200)
85 #define PPU_V0_PSR_DYNAMIC UINT32_C(0x00000100)
86 #define PPU_V0_PSR_POWSTAT UINT32_C(0x00000007)
87 
88 /*
89  * Bit definitions for IMR
90  */
91 #define PPU_V0_IMR_MASK UINT32_C(0x010000FF)
92 #define PPU_V0_IMR_STA_POLICY_TRN UINT32_C(0x00000001)
93 #define PPU_V0_IMR_STA_ACCEPT UINT32_C(0x00000002)
94 #define PPU_V0_IMR_STA_DENY UINT32_C(0x00000004)
95 #define PPU_V0_IMR_DYN_ACCEPT UINT32_C(0x00000008)
96 #define PPU_V0_IMR_DYN_DENY UINT32_C(0x00000010)
97 #define PPU_V0_IMR_EMU_ACCEPT UINT32_C(0x00000020)
98 #define PPU_V0_IMR_EMU_DENY UINT32_C(0x00000040)
99 #define PPU_V0_IMR_UNSPT_POLICY UINT32_C(0x00000080)
100 #define PPU_V0_IMR_DYN_POLICY_MIN UINT32_C(0x01000000)
101 
102 /*
103  * Bit definitions for ISR
104  */
105 #define PPU_V0_ISR_MASK UINT32_C(0x01FF01FF)
106 #define PPU_V0_ISR_STA_POLICY_TRN UINT32_C(0x00000001)
107 #define PPU_V0_ISR_STA_ACCEPT UINT32_C(0x00000002)
108 #define PPU_V0_ISR_STA_DENY UINT32_C(0x00000004)
109 #define PPU_V0_ISR_DYN_ACCEPT UINT32_C(0x00000008)
110 #define PPU_V0_ISR_DYN_DENY UINT32_C(0x00000010)
111 #define PPU_V0_ISR_EMU_ACCEPT UINT32_C(0x00000020)
112 #define PPU_V0_ISR_EMU_DENY UINT32_C(0x00000040)
113 #define PPU_V0_ISR_UNSPT_POLICY UINT32_C(0x00000080)
114 #define PPU_V0_ISR_DBGEMUPWRDWN_EDGE UINT32_C(0x00000100)
115 #define PPU_V0_ISR_ACTIVE_EDGE UINT32_C(0x00FF0000)
116 #define PPU_V0_ISR_ACTIVE_EDGE_ACTIVE0 UINT32_C(0x00010000)
117 #define PPU_V0_ISR_ACTIVE_EDGE_ACTIVE1 UINT32_C(0x00020000)
118 #define PPU_V0_ISR_ACTIVE_EDGE_ACTIVE2 UINT32_C(0x00040000)
119 #define PPU_V0_ISR_ACTIVE_EDGE_ACTIVE3 UINT32_C(0x00080000)
120 #define PPU_V0_ISR_ACTIVE_EDGE_ACTIVE4 UINT32_C(0x00100000)
121 #define PPU_V0_ISR_ACTIVE_EDGE_ACTIVE5 UINT32_C(0x00200000)
122 #define PPU_V0_ISR_ACTIVE_EDGE_ACTIVE6 UINT32_C(0x00400000)
123 #define PPU_V0_ISR_ACTIVE_EDGE_ACTIVE7 UINT32_C(0x00800000)
124 #define PPU_V0_ISR_DYN_POLICY_MIN UINT32_C(0x01000000)
125 
126 /*
127  * Bit definitions for ARCHITECTURE_ID
128  */
129 #define PPU_V0_ARCHITECTURE_ID UINT32_C(0x00000000)
130 
131 #define PPU_PCR_DEV_ACTIVE_EN UINT32_C(0x0000FF00)
132 #define PPU_PCR_DEV_REQ_EN UINT32_C(0x000000FF)
133 
134 /*
135  * Interface
136  */
137 void ppu_v0_init(struct ppu_v0_reg *ppu);
138 int ppu_v0_request_power_mode(struct ppu_v0_reg *ppu, enum ppu_v0_mode mode);
139 int ppu_v0_set_power_mode(struct ppu_v0_reg *ppu, enum ppu_v0_mode mode);
140 int ppu_v0_get_power_mode(struct ppu_v0_reg *ppu, enum ppu_v0_mode *mode);
141 
142 /*!
143  * \endcond
144  */
145 
146 #endif /* PPU_V0_H */
147