1 /* 2 * Arm SCP/MCP Software 3 * Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef SYNQUACER_DDR_H 9 #define SYNQUACER_DDR_H 10 11 #include "synquacer_mmap.h" 12 13 #include <stdbool.h> 14 #include <stdint.h> 15 16 #define DRAM_DDR4 0x00000002 17 #define DIMM_SLOT_NUM 4 18 #define SPD_BYTE_TOP_ADDR 0x00 19 #define SPD_READ_BYTE_NUM 128 20 21 #define MODULE_TYPE_RDIMM 0x01 22 #define MODULE_TYPE_UDIMM 0x02 23 #define MODULE_TYPE_72BITSOUDIMM 0x09 24 25 #define FW_MODULE_CAPACITY_16GB 0x4000 26 #define FW_MODULE_CAPACITY_8GB 0x2000 27 #define FW_MODULE_CAPACITY_4GB 0x1000 28 29 #define DDR_USE_CH0 0x1 30 #define DDR_USE_CH1 0x2 31 #define DDR_USE_DUAL_CH (DDR_USE_CH0 | DDR_USE_CH1) 32 33 #define RDIMM_16GBPERSLOT_1SLOTPERCH 0x1 34 #define RDIMM_16GBPERSLOT_2SLOTPERCH 0x2 35 #define UDIMM_4GBPERSLOT_1SLOTPERCH 0x3 36 #define SOUDIMM_72BIT_16GBPERSLOT_1SLOTPERCH 0x4 37 #define SOUDIMM_72BIT_8GBPERSLOT_1SLOTPERCH 0x5 38 #define UDIMM_8GBPERSLOT_1SLOTPERCH 0x6 39 40 #define BANK_BIT_NEXT 0x00040000 41 42 #define DRAM_AREA_1_START_ADDR UINT64_C(0x0080000000) 43 44 /* top 66MiB in DRAM1 region is reserved for Secure App */ 45 #define DRAM_RESERVED_FOR_SECURE_APP_SIZE UINT64_C(0x04200000) 46 #define DRAM_AREA_1_END_ADDR UINT64_C(0x0100000000) 47 #define DRAM_AREA_2_START_ADDR UINT64_C(0x0880000000) 48 #define DRAM_AREA_2_END_ADDR UINT64_C(0x1000000000) 49 #define DRAM_AREA_3_START_ADDR UINT64_C(0x8800000000) 50 #define DRAM_AREA_3_END_ADDR UINT64_C(0x9000000000) 51 52 #define DRAM_AREA_1_SIZE (DRAM_AREA_1_END_ADDR - DRAM_AREA_1_START_ADDR) 53 #define DRAM_AREA_2_SIZE (DRAM_AREA_2_END_ADDR - DRAM_AREA_2_START_ADDR) 54 #define DRAM_AREA_3_SIZE (DRAM_AREA_3_END_ADDR - DRAM_AREA_3_START_ADDR) 55 56 #define SPD_DTIC_SPA0 (0x36) /* set page address to 0 */ 57 #define SPD_DTIC_SPA1 (0x37) /* set page address to 1 */ 58 #define SPD_PAGE_SIZE (256) 59 #define SPD_NUM_OF_PAGE (2) 60 61 #define SPD_STORE_AREA_OFFSET (0x0000F000) 62 #define SPD_STORE_AREA_SIZE (DIMM_SLOT_NUM * (SPD_PAGE_SIZE * SPD_NUM_OF_PAGE)) 63 #define SPD_STORE_ADDR (NONTRUSTED_RAM_BASE + SPD_STORE_AREA_OFFSET) 64 65 void fw_ddr_init(void); 66 int fw_ddr_spd_param_check(void); 67 bool fw_get_ddr4_sdram_ecc_available(void); 68 uint8_t fw_get_used_memory_ch(void); 69 uint32_t fw_get_memory_type_next(void); 70 uint32_t fw_get_address_control_next(void); 71 uint32_t fw_get_ddr4_sdram_dq_map_control(uint8_t i); 72 uint32_t fw_get_ddr4_sdram_total_size(void); 73 uint32_t fw_get_memory_type(void); 74 75 #endif /* SYNQUACER_DDR_H */ 76