1 /* 2 * Arm SCP/MCP Software 3 * Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef INTERNAL_REG_PPU_H 9 #define INTERNAL_REG_PPU_H 10 11 #define PPU_BASE_AP 0x54120000 12 #define PPU_BASE_SCP 0x48120000 13 14 #define PPU_BASE PPU_BASE_SCP 15 16 #define PPU_PPR_OFFSET 0x000 17 #define PPU_PSR_OFFSET 0x004 18 #define PPU_PCR_OFFSET 0x00C 19 20 #define PPU0_BASE (PPU_BASE + 0x000) 21 #define PPU1_BASE (PPU_BASE + 0x020) 22 #define PPU2_BASE (PPU_BASE + 0x040) 23 #define PPU3_BASE (PPU_BASE + 0x060) 24 #define PPU4_BASE (PPU_BASE + 0x080) 25 #define PPU5_BASE (PPU_BASE + 0x0A0) 26 #define PPU6_BASE (PPU_BASE + 0x0C0) 27 #define PPU7_BASE (PPU_BASE + 0x0E0) 28 #define PPU8_BASE (PPU_BASE + 0x100) 29 30 #define PPU0_PPR (PPU0_BASE + PPU_PPR_OFFSET) 31 #define PPU0_PSR (PPU0_BASE + PPU_PSR_OFFSET) 32 #define PPU0_PCR (PPU0_BASE + PPU_PCR_OFFSET) 33 #define PPU1_PPR (PPU1_BASE + PPU_PPR_OFFSET) 34 #define PPU1_PSR (PPU1_BASE + PPU_PSR_OFFSET) 35 #define PPU1_PCR (PPU1_BASE + PPU_PCR_OFFSET) 36 #define PPU2_PPR (PPU2_BASE + PPU_PPR_OFFSET) 37 #define PPU2_PSR (PPU2_BASE + PPU_PSR_OFFSET) 38 #define PPU2_PCR (PPU2_BASE + PPU_PCR_OFFSET) 39 #define PPU3_PPR (PPU3_BASE + PPU_PPR_OFFSET) 40 #define PPU3_PSR (PPU3_BASE + PPU_PSR_OFFSET) 41 #define PPU3_PCR (PPU3_BASE + PPU_PCR_OFFSET) 42 #define PPU4_PPR (PPU4_BASE + PPU_PPR_OFFSET) 43 #define PPU4_PSR (PPU4_BASE + PPU_PSR_OFFSET) 44 #define PPU4_PCR (PPU4_BASE + PPU_PCR_OFFSET) 45 #define PPU5_PPR (PPU5_BASE + PPU_PPR_OFFSET) 46 #define PPU5_PSR (PPU5_BASE + PPU_PSR_OFFSET) 47 #define PPU5_PCR (PPU5_BASE + PPU_PCR_OFFSET) 48 #define PPU6_PPR (PPU6_BASE + PPU_PPR_OFFSET) 49 #define PPU6_PSR (PPU6_BASE + PPU_PSR_OFFSET) 50 #define PPU6_PCR (PPU6_BASE + PPU_PCR_OFFSET) 51 #define PPU7_PPR (PPU7_BASE + PPU_PPR_OFFSET) 52 #define PPU7_PSR (PPU7_BASE + PPU_PSR_OFFSET) 53 #define PPU7_PCR (PPU7_BASE + PPU_PCR_OFFSET) 54 #define PPU8_PPR (PPU8_BASE + PPU_PPR_OFFSET) 55 #define PPU8_PSR (PPU8_BASE + PPU_PSR_OFFSET) 56 #define PPU8_PCR (PPU8_BASE + PPU_PCR_OFFSET) 57 #define PPU_HWCACTIVE_SR (PPU_BASE + 0x800) 58 #define PPU_WFI_WFE_SR (PPU_BASE + 0x804) 59 #define PPU_PID_4 (PPU_BASE + 0xFD0) 60 #define PPU_PID_0 (PPU_BASE + 0xFE0) 61 #define PPU_PID_1 (PPU_BASE + 0xFE4) 62 #define PPU_PID_2 (PPU_BASE + 0xFE8) 63 #define PPU_PID_3 (PPU_BASE + 0xFEC) 64 #define PPU_COMP_ID0 (PPU_BASE + 0xFF0) 65 #define PPU_COMP_ID1 (PPU_BASE + 0xFF4) 66 #define PPU_COMP_ID2 (PPU_BASE + 0xFF8) 67 #define PPU_COMP_ID3 (PPU_BASE + 0xFFC) 68 69 #endif /* INTERNAL_REG_PPU_H */ 70