1 /*
2  * Arm SCP/MCP Software
3  * Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved.
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 
8 #ifndef CLOCK_SOC_H
9 #define CLOCK_SOC_H
10 
11 #include <fwk_macros.h>
12 
13 #define CLOCK_RATE_REFCLK    (100UL * FWK_MHZ)
14 #define CLOCK_RATE_SYSPLLCLK (2000UL * FWK_MHZ)
15 
16 /*
17  * PLL clock indexes.
18  */
19 enum clock_pll_idx {
20     CLOCK_PLL_IDX_CPU_CORTEX_A510,
21     CLOCK_PLL_IDX_CPU_CORTEX_A715,
22     CLOCK_PLL_IDX_CPU_CORTEX_X3,
23     CLOCK_PLL_IDX_SYS,
24     CLOCK_PLL_IDX_DPU,
25     CLOCK_PLL_IDX_PIX0,
26     CLOCK_PLL_IDX_PIX1,
27     CLOCK_PLL_IDX_COUNT
28 };
29 
30 /*
31  * PIK clock indexes.
32  */
33 enum clock_pik_idx {
34     CLOCK_PIK_IDX_CLUS0_CPU0,
35     CLOCK_PIK_IDX_CLUS0_CPU1,
36     CLOCK_PIK_IDX_CLUS0_CPU2,
37     CLOCK_PIK_IDX_CLUS0_CPU3,
38     CLOCK_PIK_IDX_CLUS0_CPU4,
39     CLOCK_PIK_IDX_CLUS0_CPU5,
40     CLOCK_PIK_IDX_CLUS0_CPU6,
41     CLOCK_PIK_IDX_CLUS0_CPU7,
42     CLOCK_PIK_IDX_GIC,
43     CLOCK_PIK_IDX_PCLKSCP,
44     CLOCK_PIK_IDX_SYSPERCLK,
45     CLOCK_PIK_IDX_UARTCLK,
46     CLOCK_PIK_IDX_DPU,
47     CLOCK_PIK_IDX_COUNT
48 };
49 
50 /*!
51  * \brief Selectable clock sources for TC1 cluster clocks.
52  */
53 enum mod_clusclock_source_tc1 {
54     /*! The clock is gated */
55     MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC1_GATED = 0x0,
56     /*! The clock source is set to the system reference clock */
57     MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC1_SYSREFCLK = 0x1,
58     /*! The clock source is set to a private cluster PLL */
59     MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC1_PLL0 = 0x2,
60     /*! The clock source is set to a private cluster PLL */
61     MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC1_PLL1 = 0x4,
62     /*! The clock source is set to a private cluster PLL */
63     MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC1_PLL2 = 0x8,
64     /*! The clock source is set to a private cluster PLL */
65     MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC1_PLL3 = 0x10,
66     /*! Number of valid clock sources */
67     MOD_PIK_CLOCK_CLUSCLK_SOURCE_TC1_MAX
68 };
69 
70 /*
71  * CSS clock indexes.
72  */
73 enum clock_css_idx {
74     CLOCK_CSS_IDX_CPU_GROUP_CORTEX_A510,
75     CLOCK_CSS_IDX_CPU_GROUP_CORTEX_A715,
76     CLOCK_CSS_IDX_CPU_GROUP_CORTEX_X3,
77     CLOCK_CSS_IDX_DPU,
78     CLOCK_CSS_IDX_COUNT
79 };
80 
81 /*
82  * Clock indexes.
83  */
84 enum clock_idx {
85     CLOCK_IDX_CPU_GROUP_CORTEX_A510,
86     CLOCK_IDX_CPU_GROUP_CORTEX_A715,
87     CLOCK_IDX_CPU_GROUP_CORTEX_X3,
88     CLOCK_IDX_DPU,
89     CLOCK_IDX_PIXEL_0,
90     CLOCK_IDX_PIXEL_1,
91     CLOCK_IDX_COUNT
92 };
93 
94 #endif /* CLOCK_SOC_H */
95