1 /*
2  * Arm SCP/MCP Software
3  * Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved.
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 
8 #ifndef FMW_CMSIS_H
9 #define FMW_CMSIS_H
10 
11 #include <stdint.h>
12 
13 #define __CHECK_DEVICE_DEFINES
14 #define __CM3_REV              0x0201
15 #define __FPU_PRESENT          0U
16 #define __MPU_PRESENT          1U
17 #define __ICACHE_PRESENT       0U
18 #define __DCACHE_PRESENT       0U
19 #define __DTCM_PRESENT         0U
20 #define __NVIC_PRIO_BITS       3U
21 #define __Vendor_SysTickConfig 0U
22 #define __VTOR_PRESENT         1U
23 
24 extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock)*/
25 
26 typedef enum IRQn {
27     Reset_IRQn = -15,
28     NonMaskableInt_IRQn = -14,
29     HardFault_IRQn = -13,
30     MemoryManagement_IRQn = -12,
31     BusFault_IRQn = -11,
32     UsageFault_IRQn = -10,
33     SVCall_IRQn = -5,
34     DebugMonitor_IRQn = -4,
35     PendSV_IRQn = -2,
36     SysTick_IRQn = -1,
37 
38     SOC_WAKEUP0_IRQ = 16, /* SoC Expansion Wakeup */
39     TIMREFCLK_IRQ = 33, /* REFCLK Physical Timer */
40     MHU_AP_NONSEC_HP_IRQ = 34, /* MHU High Priority Non-Secure */
41     MHU_AP_NONSEC_LP_IRQ = 35, /* MHU Low Priority Non-Secure */
42     MHU_AP_SEC_IRQ = 36, /* MHU Secure */
43 
44     IRQn_MAX = INT16_MAX,
45 } IRQn_Type;
46 
47 #include <core_cm3.h>
48 
49 #endif /* FMW_CMSIS_H */
50