1 /*
2 * Arm SCP/MCP Software
3 * Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #include "clock_soc.h"
9 #include "scp_mmap.h"
10 #include "scp_pik.h"
11
12 #include <mod_system_pll.h>
13
14 #include <fwk_element.h>
15 #include <fwk_id.h>
16 #include <fwk_macros.h>
17 #include <fwk_module.h>
18
19 static const struct fwk_element system_pll_element_table[
20 CLOCK_PLL_IDX_COUNT + 1] =
21 {
22 [CLOCK_PLL_IDX_CPU_CORTEX_A510] =
23 {
24 .name = "CPU_PLL_CORTEX_A510",
25 .data = &((struct mod_system_pll_dev_config){
26 .control_reg = (void *)SCP_PLL_CPU0,
27 .status_reg = (void *)&SCP_PIK_PTR->PLL_STATUS[1],
28 .lock_flag_mask = PLL_STATUS_CPUPLL_LOCK(0),
29 .initial_rate = 1537 * FWK_MHZ,
30 .min_rate = MOD_SYSTEM_PLL_MIN_RATE,
31 .max_rate = MOD_SYSTEM_PLL_MAX_RATE,
32 .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL,
33 }),
34 },
35 [CLOCK_PLL_IDX_CPU_CORTEX_A715] =
36 {
37 .name = "CPU_PLL_CORTEX_A715",
38 .data = &((struct mod_system_pll_dev_config){
39 .control_reg = (void *)SCP_PLL_CPU1,
40 .status_reg = (void *)&SCP_PIK_PTR->PLL_STATUS[1],
41 .lock_flag_mask = PLL_STATUS_CPUPLL_LOCK(4),
42 .initial_rate = 1893 * FWK_MHZ,
43 .min_rate = MOD_SYSTEM_PLL_MIN_RATE,
44 .max_rate = MOD_SYSTEM_PLL_MAX_RATE,
45 .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL,
46 }),
47 },
48 [CLOCK_PLL_IDX_CPU_CORTEX_X3] =
49 {
50 .name = "CPU_PLL_CORTEX_X3",
51 .data = &((struct mod_system_pll_dev_config){
52 .control_reg = (void *)SCP_PLL_CPU2,
53 .status_reg = (void *)&SCP_PIK_PTR->PLL_STATUS[1],
54 .lock_flag_mask = PLL_STATUS_CPUPLL_LOCK(7),
55 .initial_rate = 2176 * FWK_MHZ,
56 .min_rate = MOD_SYSTEM_PLL_MIN_RATE,
57 .max_rate = MOD_SYSTEM_PLL_MAX_RATE,
58 .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL,
59 }),
60 },
61 [CLOCK_PLL_IDX_SYS] =
62 {
63 .name = "SYS_PLL",
64 .data = &((struct mod_system_pll_dev_config){
65 .control_reg = (void *)SCP_PLL_SYSPLL,
66 .status_reg = (void *)&SCP_PIK_PTR->PLL_STATUS[0],
67 .lock_flag_mask = PLL_STATUS_0_SYSPLL_LOCK,
68 .initial_rate = 2000 * FWK_MHZ,
69 .min_rate = MOD_SYSTEM_PLL_MIN_RATE,
70 .max_rate = MOD_SYSTEM_PLL_MAX_RATE,
71 .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL,
72 }),
73 },
74 [CLOCK_PLL_IDX_DPU] =
75 {
76 .name = "DPU_PLL",
77 .data = &((struct mod_system_pll_dev_config){
78 .control_reg = (void *)SCP_PLL_DISPLAY,
79 .status_reg = (void *)&SCP_PIK_PTR->PLL_STATUS[0],
80 .lock_flag_mask = PLL_STATUS_0_DISPLAYPLL_LOCK,
81 .initial_rate = 600 * FWK_MHZ,
82 .min_rate = MOD_SYSTEM_PLL_MIN_RATE,
83 .max_rate = MOD_SYSTEM_PLL_MAX_RATE,
84 .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL,
85 .defer_initialization = false,
86 }),
87 },
88 [CLOCK_PLL_IDX_PIX0] =
89 {
90 .name = "PIX0_PLL",
91 .data = &((struct mod_system_pll_dev_config){
92 .control_reg = (void *)SCP_PLL_PIX0,
93 .status_reg = NULL,
94 .initial_rate = 594 * FWK_MHZ,
95 .min_rate = 12500 * FWK_KHZ,
96 .max_rate = 594 * FWK_MHZ,
97 .min_step = 25 * FWK_KHZ,
98 .defer_initialization = false,
99 }),
100 },
101 [CLOCK_PLL_IDX_PIX1] =
102 {
103 .name = "PIX1_PLL",
104 .data = &(
105 (struct mod_system_pll_dev_config){
106 .control_reg = (void *)SCP_PLL_PIX1,
107 .status_reg = NULL,
108 .initial_rate = 594 * FWK_MHZ,
109 .min_rate = 12500 * FWK_KHZ,
110 .max_rate = 594 * FWK_MHZ,
111 .min_step = 25 * FWK_KHZ,
112 .defer_initialization = false,
113 }),
114 },
115 [CLOCK_PLL_IDX_COUNT] = { 0 }, /* Termination description. */
116 };
117
system_pll_get_element_table(fwk_id_t module_id)118 static const struct fwk_element *system_pll_get_element_table(
119 fwk_id_t module_id)
120 {
121 return system_pll_element_table;
122 }
123
124 const struct fwk_module_config config_system_pll = {
125 .elements = FWK_MODULE_DYNAMIC_ELEMENTS(system_pll_get_element_table),
126 };
127