1 /*
2  * Arm SCP/MCP Software
3  * Copyright (c) 2022, Arm Limited and Contributors. All rights reserved.
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  *
7  * Description:
8  *     SCP PIK registers
9  */
10 
11 #ifndef SCP_PIK_H
12 #define SCP_PIK_H
13 
14 #include "scp_mmap.h"
15 
16 #include <fwk_macros.h>
17 
18 #include <stdint.h>
19 
20 struct pik_scp_reg {
21     uint32_t RESERVED0[4];
22     FWK_RW uint32_t RESET_SYNDROME;
23     FWK_RW uint32_t WIC_CTRL;
24     FWK_R uint32_t WIC_STATUS;
25     uint8_t RESERVED1[0xA00 - 0x1C];
26     FWK_R uint32_t CLKFORCE_STATUS;
27     FWK_RW uint32_t CLKFORCE_SET;
28     FWK_RW uint32_t CLKFORCE_CLR;
29     uint32_t RESERVED2;
30     FWK_R uint32_t PLL_STATUS[2];
31     uint8_t RESERVED3[0xFC0 - 0xA18];
32     FWK_R uint32_t PIK_CONFIG;
33     uint32_t RESERVED4[3];
34     FWK_R uint32_t PID4;
35     FWK_R uint32_t PID5;
36     FWK_R uint32_t PID6;
37     FWK_R uint32_t PID7;
38     FWK_R uint32_t PID0;
39     FWK_R uint32_t PID1;
40     FWK_R uint32_t PID2;
41     FWK_R uint32_t PID3;
42     FWK_R uint32_t ID0;
43     FWK_R uint32_t ID1;
44     FWK_R uint32_t ID2;
45     FWK_R uint32_t ID3;
46 };
47 
48 #define PLL_STATUS_0_SYSPLL_LOCK     UINT32_C(1 << 5)
49 #define PLL_STATUS_0_DISPLAYPLL_LOCK UINT32_C(1 << 6)
50 
51 #define PLL_STATUS_CPUPLL_LOCK(CPU) ((uint32_t)(1 << (CPU % 32)))
52 
53 /* Pointer to SCP PIK */
54 #define SCP_PIK_PTR ((struct pik_scp_reg *)SCP_PIK_SCP_BASE)
55 
56 #endif /* SCP_PIK_H */
57