1/*
2 * Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <common/bl_common.ld.h>
8#include <lib/xlat_tables/xlat_tables_defs.h>
9
10OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
11OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
12ENTRY(bl2_entrypoint)
13
14MEMORY {
15#if BL2_IN_XIP_MEM
16    ROM (rx): ORIGIN = BL2_RO_BASE, LENGTH = BL2_RO_LIMIT - BL2_RO_BASE
17    RAM (rwx): ORIGIN = BL2_RW_BASE, LENGTH = BL2_RW_LIMIT - BL2_RW_BASE
18#else
19    RAM (rwx): ORIGIN = BL2_BASE, LENGTH = BL2_LIMIT - BL2_BASE
20#endif
21#if SEPARATE_BL2_NOLOAD_REGION
22    RAM_NOLOAD (rw!a): ORIGIN = BL2_NOLOAD_START, LENGTH = BL2_NOLOAD_LIMIT - BL2_NOLOAD_START
23#else
24#define RAM_NOLOAD RAM
25#endif
26}
27
28#if !BL2_IN_XIP_MEM
29#define ROM RAM
30#endif
31
32SECTIONS
33{
34#if BL2_IN_XIP_MEM
35    . = BL2_RO_BASE;
36    ASSERT(. == ALIGN(PAGE_SIZE),
37           "BL2_RO_BASE address is not aligned on a page boundary.")
38#else
39    . = BL2_BASE;
40    ASSERT(. == ALIGN(PAGE_SIZE),
41           "BL2_BASE address is not aligned on a page boundary.")
42#endif
43
44#if SEPARATE_CODE_AND_RODATA
45    .text . : {
46        __TEXT_START__ = .;
47	__TEXT_RESIDENT_START__ = .;
48	*bl2_el3_entrypoint.o(.text*)
49	*(.text.asm.*)
50	__TEXT_RESIDENT_END__ = .;
51        *(SORT_BY_ALIGNMENT(.text*))
52        *(.vectors)
53        . = ALIGN(PAGE_SIZE);
54        __TEXT_END__ = .;
55     } >ROM
56
57    .rodata . : {
58        __RODATA_START__ = .;
59        *(SORT_BY_ALIGNMENT(.rodata*))
60
61	RODATA_COMMON
62
63        . = ALIGN(PAGE_SIZE);
64        __RODATA_END__ = .;
65    } >ROM
66
67    ASSERT(__TEXT_RESIDENT_END__ - __TEXT_RESIDENT_START__ <= PAGE_SIZE,
68          "Resident part of BL2 has exceeded its limit.")
69#else
70    ro . : {
71        __RO_START__ = .;
72	__TEXT_RESIDENT_START__ = .;
73	*bl2_el3_entrypoint.o(.text*)
74	*(.text.asm.*)
75	__TEXT_RESIDENT_END__ = .;
76        *(SORT_BY_ALIGNMENT(.text*))
77        *(SORT_BY_ALIGNMENT(.rodata*))
78
79	RODATA_COMMON
80
81        *(.vectors)
82        __RO_END_UNALIGNED__ = .;
83        /*
84         * Memory page(s) mapped to this section will be marked as
85         * read-only, executable.  No RW data from the next section must
86         * creep in.  Ensure the rest of the current memory page is unused.
87         */
88        . = ALIGN(PAGE_SIZE);
89
90        __RO_END__ = .;
91    } >ROM
92#endif
93
94    ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__,
95          "cpu_ops not defined for this platform.")
96
97#if BL2_IN_XIP_MEM
98    . = BL2_RW_BASE;
99    ASSERT(BL2_RW_BASE == ALIGN(PAGE_SIZE),
100           "BL2_RW_BASE address is not aligned on a page boundary.")
101#endif
102
103    /*
104     * Define a linker symbol to mark start of the RW memory area for this
105     * image.
106     */
107    __RW_START__ = . ;
108
109    DATA_SECTION >RAM AT>ROM
110    __DATA_RAM_START__ = __DATA_START__;
111    __DATA_RAM_END__ = __DATA_END__;
112
113    RELA_SECTION >RAM
114#if SEPARATE_BL2_NOLOAD_REGION
115    SAVED_ADDR = .;
116    . = BL2_NOLOAD_START;
117    __BL2_NOLOAD_START__ = .;
118#endif
119    STACK_SECTION >RAM_NOLOAD
120    BSS_SECTION >RAM_NOLOAD
121    XLAT_TABLE_SECTION >RAM_NOLOAD
122#if SEPARATE_BL2_NOLOAD_REGION
123    __BL2_NOLOAD_END__ = .;
124    . = SAVED_ADDR;
125#endif
126
127#if USE_COHERENT_MEM
128    /*
129     * The base address of the coherent memory section must be page-aligned (4K)
130     * to guarantee that the coherent data are stored on their own pages and
131     * are not mixed with normal data.  This is required to set up the correct
132     * memory attributes for the coherent data page tables.
133     */
134    coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) {
135        __COHERENT_RAM_START__ = .;
136        *(tzfw_coherent_mem)
137        __COHERENT_RAM_END_UNALIGNED__ = .;
138        /*
139         * Memory page(s) mapped to this section will be marked
140         * as device memory.  No other unexpected data must creep in.
141         * Ensure the rest of the current memory page is unused.
142         */
143        . = ALIGN(PAGE_SIZE);
144        __COHERENT_RAM_END__ = .;
145    } >RAM
146#endif
147
148    /*
149     * Define a linker symbol to mark end of the RW memory area for this
150     * image.
151     */
152    __RW_END__ = .;
153    __BL2_END__ = .;
154
155    /DISCARD/ : {
156        *(.dynsym .dynstr .hash .gnu.hash)
157    }
158
159#if BL2_IN_XIP_MEM
160    __BL2_RAM_START__ = ADDR(.data);
161    __BL2_RAM_END__ = .;
162
163    __DATA_ROM_START__ = LOADADDR(.data);
164    __DATA_SIZE__ = SIZEOF(.data);
165
166    /*
167     * The .data section is the last PROGBITS section so its end marks the end
168     * of BL2's RO content in XIP memory..
169     */
170    __BL2_ROM_END__ =  __DATA_ROM_START__ + __DATA_SIZE__;
171    ASSERT(__BL2_ROM_END__ <= BL2_RO_LIMIT,
172           "BL2's RO content has exceeded its limit.")
173#endif
174    __BSS_SIZE__ = SIZEOF(.bss);
175
176
177#if USE_COHERENT_MEM
178    __COHERENT_RAM_UNALIGNED_SIZE__ =
179        __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
180#endif
181
182#if BL2_IN_XIP_MEM
183    ASSERT(. <= BL2_RW_LIMIT, "BL2's RW content has exceeded its limit.")
184#else
185    ASSERT(. <= BL2_LIMIT, "BL2 image has exceeded its limit.")
186#endif
187}
188