1/*
2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <asm_macros.S>
8
9	.globl	wa_cve_2017_5715_icache_inv_vbar
10
11vector_base wa_cve_2017_5715_icache_inv_vbar
12	/* We encode the exception entry in the bottom 3 bits of SP */
13	add	sp, sp, #1	/* Reset: 0b111 */
14	add	sp, sp, #1	/* Undef: 0b110 */
15	add	sp, sp, #1	/* Syscall: 0b101 */
16	add	sp, sp, #1	/* Prefetch abort: 0b100 */
17	add	sp, sp, #1	/* Data abort: 0b011 */
18	add	sp, sp, #1	/* Reserved: 0b010 */
19	add	sp, sp, #1	/* IRQ: 0b001 */
20	nop			/* FIQ: 0b000 */
21
22	/*
23	 * Invalidate the instruction cache, which we assume also
24	 * invalidates the branch predictor.  This may depend on
25	 * other CPU specific changes (e.g. an ACTLR setting).
26	 */
27	stcopr	r0, ICIALLU
28	isb
29
30	/*
31	 * As we cannot use any temporary registers and cannot
32	 * clobber SP, we can decode the exception entry using
33	 * an unrolled binary search.
34	 *
35	 * Note, if this code is re-used by other secure payloads,
36	 * the below exception entry vectors must be changed to
37	 * the vectors specific to that secure payload.
38	 */
39
40	tst	sp, #4
41	bne	1f
42
43	tst	sp, #2
44	bne	3f
45
46	/* Expected encoding: 0x1 and 0x0 */
47	tst	sp, #1
48	/* Restore original value of SP by clearing the bottom 3 bits */
49	bic	sp, sp, #0x7
50	bne	plat_panic_handler	/* IRQ */
51	b	sp_min_handle_fiq	/* FIQ */
52
531:
54	/* Expected encoding: 0x4 and 0x5 */
55	tst	sp, #2
56	bne	2f
57
58	tst	sp, #1
59	bic	sp, sp, #0x7
60	bne	sp_min_handle_smc	/* Syscall */
61	b	plat_panic_handler	/* Prefetch abort */
62
632:
64	/* Expected encoding: 0x7 and 0x6 */
65	tst	sp, #1
66	bic	sp, sp, #0x7
67	bne	sp_min_entrypoint	/* Reset */
68	b	plat_panic_handler	/* Undef */
69
703:
71	/* Expected encoding: 0x2 and 0x3 */
72	tst	sp, #1
73	bic	sp, sp, #0x7
74	bne	plat_panic_handler	/* Data abort */
75	b	plat_panic_handler	/* Reserved */
76