1Maximum Power Mitigation Mechanism (MPMM)
2^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
3
4|MPMM| is an optional microarchitectural power management mechanism supported by
5some Arm Armv9-A cores, beginning with the Cortex-X2, Cortex-A710 and
6Cortex-A510 cores. This mechanism detects and limits high-activity events to
7assist in |SoC| processor power domain dynamic power budgeting and limit the
8triggering of whole-rail (i.e. clock chopping) responses to overcurrent
9conditions.
10
11|MPMM| is enabled on a per-core basis by the EL3 runtime firmware. The presence
12of |MPMM| cannot be determined at runtime by the firmware, and therefore the
13platform must expose this information through one of two possible mechanisms:
14
15- |FCONF|, controlled by the ``ENABLE_MPMM_FCONF`` build option.
16- A platform implementation of the ``plat_mpmm_topology`` function (the
17  default).
18
19See :ref:`Maximum Power Mitigation Mechanism (MPMM) Bindings` for documentation
20on the |FCONF| device tree bindings.
21
22.. warning::
23
24    |MPMM| exposes gear metrics through the auxiliary |AMU| counters. An
25    external power controller can use these metrics to budget SoC power by
26    limiting the number of cores that can execute higher-activity workloads or
27    switching to a different DVFS operating point. When this is the case, the
28    |AMU| counters that make up the |MPMM| gears must be enabled by the EL3
29    runtime firmware - please see :ref:`Activity Monitor Auxiliary Counters` for
30    documentation on enabling auxiliary |AMU| counters.
31