1Allwinner ARMv8 SoCs 2==================== 3 4Trusted Firmware-A (TF-A) implements the EL3 firmware layer for Allwinner 5SoCs with ARMv8 cores. Only BL31 is used to provide proper EL3 setup and 6PSCI runtime services. 7 8Building TF-A 9------------- 10 11There is one build target per supported SoC: 12 13+------+-------------------+ 14| SoC | TF-A build target | 15+======+===================+ 16| A64 | sun50i_a64 | 17+------+-------------------+ 18| H5 | sun50i_a64 | 19+------+-------------------+ 20| H6 | sun50i_h6 | 21+------+-------------------+ 22| H616 | sun50i_h616 | 23+------+-------------------+ 24| H313 | sun50i_h616 | 25+------+-------------------+ 26| R329 | sun50i_r329 | 27+------+-------------------+ 28 29To build with the default settings for a particular SoC: 30 31.. code:: shell 32 33 make CROSS_COMPILE=aarch64-linux-gnu- PLAT=<build target> DEBUG=1 34 35So for instance to build for a board with the Allwinner A64 SoC:: 36 37 make CROSS_COMPILE=aarch64-linux-gnu- PLAT=sun50i_a64 DEBUG=1 38 39Platform-specific build options 40~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 41 42The default build options should generate a working firmware image. There are 43some build options that allow to fine-tune the firmware, or to disable support 44for optional features. 45 46- ``SUNXI_PSCI_USE_NATIVE`` : Support direct control of the CPU cores powerdown 47 and powerup sequence by BL31. This requires either support for a code snippet 48 to be loaded into the ARISC SCP (A64, H5), or the power sequence control 49 registers to be programmed directly (H6, H616). This supports only basic 50 control, like core on/off and system off/reset. 51 This option defaults to 1. If an active SCP supporting the SCPI protocol 52 is detected at runtime, this control scheme will be ignored, and SCPI 53 will be used instead, unless support has been explicitly disabled. 54 55- ``SUNXI_PSCI_USE_SCPI`` : Support control of the CPU cores powerdown and 56 powerup sequence by talking to the SCP processor via the SCPI protocol. 57 This allows more advanced power saving techniques, like suspend to RAM. 58 This option defaults to 1 on SoCs that feature an SCP. If no SCP firmware 59 using the SCPI protocol is detected, the native sequence will be used 60 instead. If both native and SCPI methods are included, SCPI will be favoured 61 if SCP support is detected. 62 63- ``SUNXI_SETUP_REGULATORS`` : On SoCs that typically ship with a PMIC 64 power management controller, BL31 tries to set up all needed power rails, 65 programming them to their respective voltages. That allows bootloader 66 software like U-Boot to ignore power control via the PMIC. 67 This setting defaults to 1. In some situations that enables too many 68 regulators, or some regulators need to be enabled in a very specific 69 sequence. To avoid problems with those boards, ``SUNXI_SETUP_REGULATORS`` 70 can bet set to ``0`` on the build command line, to skip the PMIC setup 71 entirely. Any bootloader or OS would need to setup the PMIC on its own then. 72 73Installation 74------------ 75 76U-Boot's SPL acts as a loader, loading both BL31 and BL33 (typically U-Boot). 77Loading is done from SD card, eMMC or SPI flash, also via an USB debug 78interface (FEL). 79 80After building bl31.bin, the binary must be fed to the U-Boot build system 81to include it in the FIT image that the SPL loader will process. 82bl31.bin can be either copied (or sym-linked) into U-Boot's root directory, 83or the environment variable BL31 must contain the binary's path. 84See the respective `U-Boot documentation`_ for more details. 85 86.. _U-Boot documentation: https://gitlab.denx.de/u-boot/u-boot/-/blob/master/board/sunxi/README.sunxi64 87 88Memory layout 89------------- 90 91A64, H5 and H6 SoCs 92~~~~~~~~~~~~~~~~~~~ 93 94BL31 lives in SRAM A2, which is documented to be accessible from secure 95world only. Since this SRAM region is very limited (48 KB), we take 96several measures to reduce memory consumption. One of them is to confine 97BL31 to only 28 bits of virtual address space, which reduces the number 98of required page tables (each occupying 4KB of memory). 99The mapping we use on those SoCs is as follows: 100 101:: 102 103 0 64K 16M 1GB 1G+160M physical address 104 +-+------+-+---+------+--...---+-------+----+------+---------- 105 |B| |S|///| |//...///| |////| | 106 |R| SRAM |C|///| dev |//...///| (sec) |////| BL33 | DRAM ... 107 |O| |P|///| MMIO |//...///| DRAM |////| | 108 |M| | |///| |//...///| (32M) |////| | 109 +-+------+-+---+------+--...---+-------+----+------+---------- 110 | | | | | | / / / / 111 | | | | | | / / / / 112 | | | | | | / / / / 113 | | | | | | / // / 114 | | | | | | / / / 115 +-+------+-+---+------+--+-------+------+ 116 |B| |S|///| |//| | | 117 |R| SRAM |C|///| dev |//| sec | BL33 | 118 |O| |P|///| MMIO |//| DRAM | | 119 |M| | |///| |//| | | 120 +-+------+-+---+------+--+-------+------+ 121 0 64K 16M 160M 192M 256M virtual address 122 123 124H616 SoC 125~~~~~~~~ 126 127The H616 lacks the secure SRAM region present on the other SoCs, also 128lacks the "ARISC" management processor (SCP) we use. BL31 thus needs to 129run from DRAM, which prevents our compressed virtual memory map described 130above. Since running in DRAM also lifts the restriction of the limited 131SRAM size, we use the normal 1:1 mapping with 32 bits worth of virtual 132address space. So the virtual addresses used in BL31 match the physical 133addresses as presented above. 134 135Trusted OS dispatcher 136--------------------- 137 138One can boot Trusted OS(OP-TEE OS, bl32 image) along side bl31 image on Allwinner A64. 139 140In order to include the 'opteed' dispatcher in the image, pass 'SPD=opteed' on the command line 141while compiling the bl31 image and make sure the loader (SPL) loads the Trusted OS binary to 142the beginning of DRAM (0x40000000). 143