1 /*
2 * Copyright (C) 2018-2021 Marvell International Ltd.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 * https://spdx.org/licenses
6 */
7
8 /* Marvell CP110 ana A3700 common */
9
10 #ifndef PHY_COMPHY_COMMON_H
11 #define PHY_COMPHY_COMMON_H
12
13 /* #define DEBUG_COMPHY */
14 #ifdef DEBUG_COMPHY
15 #define debug(format...) printf(format)
16 #else
17 #define debug(format, arg...)
18 #endif
19
20 /* A lane is described by 4 fields:
21 * - bit 1~0 represent comphy polarity invert
22 * - bit 7~2 represent comphy speed
23 * - bit 11~8 represent unit index
24 * - bit 16~12 represent mode
25 * - bit 17 represent comphy indication of clock source
26 * - bit 20~18 represents pcie width (in case of pcie comphy config.)
27 * - bit 21 represents the source of the request (Linux/Bootloader),
28 * (reguired only for PCIe!)
29 * - bit 31~22 reserved
30 */
31
32 #define COMPHY_INVERT_OFFSET 0
33 #define COMPHY_INVERT_LEN 2
34 #define COMPHY_INVERT_MASK COMPHY_MASK(COMPHY_INVERT_OFFSET, \
35 COMPHY_INVERT_LEN)
36 #define COMPHY_SPEED_OFFSET (COMPHY_INVERT_OFFSET + COMPHY_INVERT_LEN)
37 #define COMPHY_SPEED_LEN 6
38 #define COMPHY_SPEED_MASK COMPHY_MASK(COMPHY_SPEED_OFFSET, \
39 COMPHY_SPEED_LEN)
40 #define COMPHY_UNIT_ID_OFFSET (COMPHY_SPEED_OFFSET + COMPHY_SPEED_LEN)
41 #define COMPHY_UNIT_ID_LEN 4
42 #define COMPHY_UNIT_ID_MASK COMPHY_MASK(COMPHY_UNIT_ID_OFFSET, \
43 COMPHY_UNIT_ID_LEN)
44 #define COMPHY_MODE_OFFSET (COMPHY_UNIT_ID_OFFSET + COMPHY_UNIT_ID_LEN)
45 #define COMPHY_MODE_LEN 5
46 #define COMPHY_MODE_MASK COMPHY_MASK(COMPHY_MODE_OFFSET, COMPHY_MODE_LEN)
47 #define COMPHY_CLK_SRC_OFFSET (COMPHY_MODE_OFFSET + COMPHY_MODE_LEN)
48 #define COMPHY_CLK_SRC_LEN 1
49 #define COMPHY_CLK_SRC_MASK COMPHY_MASK(COMPHY_CLK_SRC_OFFSET, \
50 COMPHY_CLK_SRC_LEN)
51 #define COMPHY_PCI_WIDTH_OFFSET (COMPHY_CLK_SRC_OFFSET + COMPHY_CLK_SRC_LEN)
52 #define COMPHY_PCI_WIDTH_LEN 3
53 #define COMPHY_PCI_WIDTH_MASK COMPHY_MASK(COMPHY_PCI_WIDTH_OFFSET, \
54 COMPHY_PCI_WIDTH_LEN)
55 #define COMPHY_PCI_CALLER_OFFSET \
56 (COMPHY_PCI_WIDTH_OFFSET + COMPHY_PCI_WIDTH_LEN)
57 #define COMPHY_PCI_CALLER_LEN 1
58 #define COMPHY_PCI_CALLER_MASK COMPHY_MASK(COMPHY_PCI_CALLER_OFFSET, \
59 COMPHY_PCI_CALLER_LEN)
60
61 #define COMPHY_MASK(offset, len) (((1 << (len)) - 1) << (offset))
62
63 /* Macro which extracts mode from lane description */
64 #define COMPHY_GET_MODE(x) (((x) & COMPHY_MODE_MASK) >> \
65 COMPHY_MODE_OFFSET)
66 /* Macro which extracts unit index from lane description */
67 #define COMPHY_GET_ID(x) (((x) & COMPHY_UNIT_ID_MASK) >> \
68 COMPHY_UNIT_ID_OFFSET)
69 /* Macro which extracts speed from lane description */
70 #define COMPHY_GET_SPEED(x) (((x) & COMPHY_SPEED_MASK) >> \
71 COMPHY_SPEED_OFFSET)
72 /* Macro which extracts clock source indication from lane description */
73 #define COMPHY_GET_CLK_SRC(x) (((x) & COMPHY_CLK_SRC_MASK) >> \
74 COMPHY_CLK_SRC_OFFSET)
75 /* Macro which extracts pcie width indication from lane description */
76 #define COMPHY_GET_PCIE_WIDTH(x) (((x) & COMPHY_PCI_WIDTH_MASK) >> \
77 COMPHY_PCI_WIDTH_OFFSET)
78
79 /* Macro which extracts the caller for pcie power on from lane description */
80 #define COMPHY_GET_CALLER(x) (((x) & COMPHY_PCI_CALLER_MASK) >> \
81 COMPHY_PCI_CALLER_OFFSET)
82
83 /* Macro which extracts the polarity invert from lane description */
84 #define COMPHY_GET_POLARITY_INVERT(x) (((x) & COMPHY_INVERT_MASK) >> \
85 COMPHY_INVERT_OFFSET)
86
87
88 #define COMPHY_SATA_MODE 0x1
89 #define COMPHY_SGMII_MODE 0x2 /* SGMII 1G */
90 #define COMPHY_2500BASEX_MODE 0x3 /* 2500Base-X */
91 #define COMPHY_USB3H_MODE 0x4
92 #define COMPHY_USB3D_MODE 0x5
93 #define COMPHY_PCIE_MODE 0x6
94 #define COMPHY_RXAUI_MODE 0x7
95 #define COMPHY_XFI_MODE 0x8
96 #define COMPHY_SFI_MODE 0x9
97 #define COMPHY_USB3_MODE 0xa
98 #define COMPHY_AP_MODE 0xb
99
100 #define COMPHY_UNUSED 0xFFFFFFFF
101
102 /* Polarity invert macro */
103 #define COMPHY_POLARITY_NO_INVERT 0
104 #define COMPHY_POLARITY_TXD_INVERT 1
105 #define COMPHY_POLARITY_RXD_INVERT 2
106 #define COMPHY_POLARITY_ALL_INVERT (COMPHY_POLARITY_TXD_INVERT | \
107 COMPHY_POLARITY_RXD_INVERT)
108
109 enum reg_width_type {
110 REG_16BIT = 0,
111 REG_32BIT,
112 };
113
114 enum {
115 COMPHY_LANE0 = 0,
116 COMPHY_LANE1,
117 COMPHY_LANE2,
118 COMPHY_LANE3,
119 COMPHY_LANE4,
120 COMPHY_LANE5,
121 COMPHY_LANE_MAX,
122 };
123
polling_with_timeout(uintptr_t addr,uint32_t val,uint32_t mask,uint32_t usec_timeout,enum reg_width_type type)124 static inline uint32_t polling_with_timeout(uintptr_t addr, uint32_t val,
125 uint32_t mask,
126 uint32_t usec_timeout,
127 enum reg_width_type type)
128 {
129 uint32_t data;
130
131 do {
132 udelay(1);
133 if (type == REG_16BIT)
134 data = mmio_read_16(addr) & mask;
135 else
136 data = mmio_read_32(addr) & mask;
137 } while (data != val && --usec_timeout > 0);
138
139 if (usec_timeout == 0)
140 return data;
141
142 return 0;
143 }
144
reg_set(uintptr_t addr,uint32_t data,uint32_t mask)145 static inline void reg_set(uintptr_t addr, uint32_t data, uint32_t mask)
146 {
147 debug("<atf>: WR to addr = 0x%lx, data = 0x%x (mask = 0x%x) - ",
148 addr, data, mask);
149 debug("old value = 0x%x ==> ", mmio_read_32(addr));
150 mmio_clrsetbits_32(addr, mask, data & mask);
151
152 debug("new val 0x%x\n", mmio_read_32(addr));
153 }
154
reg_set16(uintptr_t addr,uint16_t data,uint16_t mask)155 static inline void __unused reg_set16(uintptr_t addr, uint16_t data,
156 uint16_t mask)
157 {
158
159 debug("<atf>: WR to addr = 0x%lx, data = 0x%x (mask = 0x%x) - ",
160 addr, data, mask);
161 debug("old value = 0x%x ==> ", mmio_read_16(addr));
162 mmio_clrsetbits_16(addr, mask, data & mask);
163
164 debug("new val 0x%x\n", mmio_read_16(addr));
165 }
166
167 #endif /* PHY_COMPHY_COMMON_H */
168