1 /*
2  * Copyright 2020-2022 NXP
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  *
6  */
7 
8 #include <common/debug.h>
9 #include "dcfg.h"
10 #include <lib/mmio.h>
11 #ifdef NXP_SFP_ENABLED
12 #include <sfp.h>
13 #endif
14 
15 static soc_info_t soc_info = {0};
16 static devdisr5_info_t devdisr5_info = {0};
17 static dcfg_init_info_t *dcfg_init_info;
18 
19 /* Read the PORSR1 register */
read_reg_porsr1(void)20 uint32_t read_reg_porsr1(void)
21 {
22 	unsigned int *porsr1_addr = NULL;
23 
24 	if (dcfg_init_info->porsr1 != 0U) {
25 		return dcfg_init_info->porsr1;
26 	}
27 
28 	porsr1_addr = (void *)
29 			(dcfg_init_info->g_nxp_dcfg_addr + DCFG_PORSR1_OFFSET);
30 	dcfg_init_info->porsr1 = gur_in32(porsr1_addr);
31 
32 	return dcfg_init_info->porsr1;
33 }
34 
35 
get_soc_info(void)36 const soc_info_t *get_soc_info(void)
37 {
38 	uint32_t reg;
39 
40 	if (soc_info.is_populated == true) {
41 		return (const soc_info_t *) &soc_info;
42 	}
43 
44 	reg = gur_in32(dcfg_init_info->g_nxp_dcfg_addr + DCFG_SVR_OFFSET);
45 
46 	soc_info.svr_reg.val = reg;
47 
48 	/* zero means SEC enabled. */
49 	soc_info.sec_enabled =
50 		(((reg & SVR_SEC_MASK) >> SVR_SEC_SHIFT) == 0) ? true : false;
51 
52 	soc_info.is_populated = true;
53 	return (const soc_info_t *) &soc_info;
54 }
55 
dcfg_init(dcfg_init_info_t * dcfg_init_data)56 void dcfg_init(dcfg_init_info_t *dcfg_init_data)
57 {
58 	dcfg_init_info = dcfg_init_data;
59 	read_reg_porsr1();
60 	get_soc_info();
61 }
62 
is_sec_enabled(void)63 bool is_sec_enabled(void)
64 {
65 	return soc_info.sec_enabled;
66 }
67 
get_devdisr5_info(void)68 const devdisr5_info_t *get_devdisr5_info(void)
69 {
70 	uint32_t reg;
71 
72 	if (devdisr5_info.is_populated == true)
73 		return (const devdisr5_info_t *) &devdisr5_info;
74 
75 	reg = gur_in32(dcfg_init_info->g_nxp_dcfg_addr + DCFG_DEVDISR5_OFFSET);
76 
77 	devdisr5_info.ddrc1_present = (reg & DISR5_DDRC1_MASK) ? 0 : 1;
78 #if defined(CONFIG_CHASSIS_3_2)
79 	devdisr5_info.ddrc2_present = (reg & DISR5_DDRC2_MASK) ? 0 : 1;
80 #endif
81 	devdisr5_info.ocram_present = (reg & DISR5_OCRAM_MASK) ? 0 : 1;
82 	devdisr5_info.is_populated = true;
83 
84 	return (const devdisr5_info_t *) &devdisr5_info;
85 }
86 
get_clocks(struct sysinfo * sys)87 int get_clocks(struct sysinfo *sys)
88 {
89 	unsigned int *rcwsr0 = NULL;
90 	const unsigned long sysclk = dcfg_init_info->nxp_sysclk_freq;
91 	const unsigned long ddrclk = dcfg_init_info->nxp_ddrclk_freq;
92 
93 	rcwsr0 = (void *)(dcfg_init_info->g_nxp_dcfg_addr + RCWSR0_OFFSET);
94 	sys->freq_platform = sysclk;
95 	sys->freq_ddr_pll0 = ddrclk;
96 	sys->freq_ddr_pll1 = ddrclk;
97 
98 	sys->freq_platform *= (gur_in32(rcwsr0) >>
99 				RCWSR0_SYS_PLL_RAT_SHIFT) &
100 				RCWSR0_SYS_PLL_RAT_MASK;
101 
102 	sys->freq_platform /= dcfg_init_info->nxp_plat_clk_divider;
103 
104 	sys->freq_ddr_pll0 *= (gur_in32(rcwsr0) >>
105 				RCWSR0_MEM_PLL_RAT_SHIFT) &
106 				RCWSR0_MEM_PLL_RAT_MASK;
107 	sys->freq_ddr_pll1 *= (gur_in32(rcwsr0) >>
108 				RCWSR0_MEM2_PLL_RAT_SHIFT) &
109 				RCWSR0_MEM2_PLL_RAT_MASK;
110 	if (sys->freq_platform == 0) {
111 		return 1;
112 	} else {
113 		return 0;
114 	}
115 }
116 
117 #ifdef NXP_SFP_ENABLED
118 /*******************************************************************************
119  * Returns true if secur eboot is enabled on board
120  * mode = 0  (development mode - sb_en = 1)
121  * mode = 1 (production mode - ITS = 1)
122  ******************************************************************************/
check_boot_mode_secure(uint32_t * mode)123 bool check_boot_mode_secure(uint32_t *mode)
124 {
125 	uint32_t val = 0U;
126 	uint32_t *rcwsr = NULL;
127 	*mode = 0U;
128 
129 	if (sfp_check_its() == 1) {
130 		/* ITS =1 , Production mode */
131 		*mode = 1U;
132 		return true;
133 	}
134 
135 	rcwsr = (void *)(dcfg_init_info->g_nxp_dcfg_addr + RCWSR_SB_EN_OFFSET);
136 
137 	val = (gur_in32(rcwsr) >> RCWSR_SBEN_SHIFT) &
138 				RCWSR_SBEN_MASK;
139 
140 	if (val == RCWSR_SBEN_MASK) {
141 		*mode = 0U;
142 		return true;
143 	}
144 
145 	return false;
146 }
147 #endif
148 
error_handler(int error_code)149 void error_handler(int error_code)
150 {
151 	 /* Dump error code in SCRATCH4 register */
152 	INFO("Error in Fuse Provisioning: %x\n", error_code);
153 	gur_out32((void *)
154 		  (dcfg_init_info->g_nxp_dcfg_addr + DCFG_SCRATCH4_OFFSET),
155 		  error_code);
156 }
157