1 /*
2 * Copyright 2022 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #ifndef IFC_H
8 #define IFC_H
9
10 #include <endian.h>
11
12 #include <mmio.h>
13
14 #define NXP_IFC_RUN_TIME_ADDR U(0x1000)
15
16 /* CPSR - Chip Select Property Register Offset */
17 #define EXT_CSPR(n) (U(0x000C) + (n * 0xC))
18 #define CSPR(n) (U(0x0010) + (n * 0xC))
19 #define CSOR(n) (U(0x0130) + (n * 0xC))
20 #define EXT_CSOR(n) (U(0x0134) + (n * 0xC))
21 #define IFC_AMASK_CS0 U(0x00A0)
22
23 /* NAND specific Registers Offset */
24 #define NCFGR (NXP_IFC_RUN_TIME_ADDR + U(0x0000))
25 #define NAND_FCR0 (NXP_IFC_RUN_TIME_ADDR + U(0x0014))
26
27 #define ROW0 (NXP_IFC_RUN_TIME_ADDR + U(0x003C))
28 #define ROW1 (NXP_IFC_RUN_TIME_ADDR + U(0x004C))
29 #define COL0 (NXP_IFC_RUN_TIME_ADDR + U(0x0044))
30 #define COL1 (NXP_IFC_RUN_TIME_ADDR + U(0x0054))
31
32 #define NAND_BC (NXP_IFC_RUN_TIME_ADDR + U(0x0108))
33 #define NAND_FIR0 (NXP_IFC_RUN_TIME_ADDR + U(0x0110))
34 #define NAND_FIR1 (NXP_IFC_RUN_TIME_ADDR + U(0x0114))
35 #define NAND_FIR2 (NXP_IFC_RUN_TIME_ADDR + U(0x0118))
36 #define NAND_CSEL (NXP_IFC_RUN_TIME_ADDR + U(0x015C))
37 #define NANDSEQ_STRT (NXP_IFC_RUN_TIME_ADDR + U(0x0164))
38 #define NAND_EVTER_STAT (NXP_IFC_RUN_TIME_ADDR + U(0x016C))
39 #define NAND_AUTOBOOT_TRGR (NXP_IFC_RUN_TIME_ADDR + U(0x0284))
40
41 /* Size of SRAM Buffer */
42 #define CSPR_PS U(0x00000180)
43 #define CSPR_PS_SHIFT 7
44 #define CSPR_PS_8 0x1 // Port Size 8 bit
45 #define CSPR_PS_16 0x2 // Port Size 16 bit
46 #define CSPR_PS_32 0x3 // Port Size 32 bit
47
48 /* Chip Select Option Register NAND Machine */
49 #define CSOR_NAND_PGS U(0x00380000)
50 #define CSOR_NAND_PGS_SHIFT 19
51 #define CSOR_NAND_PGS_512 U(0x00000000)
52 #define CSOR_NAND_PGS_2K U(0x00080000)
53 #define CSOR_NAND_PGS_4K U(0x00100000)
54 #define CSOR_NAND_PGS_8K U(0x00180000)
55 #define CSOR_NAND_PGS_16K U(0x00200000)
56
57
58 #define CSOR_NAND_PB U(0x00000700)
59 #define CSOR_NAND_PB_32 U(0x00000000)
60 #define CSOR_NAND_PB_64 U(0x00000100)
61 #define CSOR_NAND_PB_128 U(0x00000200)
62 #define CSOR_NAND_PB_256 U(0x00000300)
63 #define CSOR_NAND_PB_512 U(0x00000400)
64 #define CSOR_NAND_PB_1024 U(0x00000500)
65 #define CSOR_NAND_PB_2048 U(0x00000600)
66 #define CSOR_NAND_PPB_32 32
67 #define CSOR_NAND_PPB_64 64
68 #define CSOR_NAND_PPB_128 128
69 #define CSOR_NAND_PPB_256 256
70 #define CSOR_NAND_PPB_512 512
71 #define CSOR_NAND_PPB_1024 1024
72 #define CSOR_NAND_PPB_2048 2048
73
74 /* NAND Chip select register */
75 #define NAND_CSEL_SHIFT 26
76 #define NAND_COL_MS_SHIFT 31
77
78 /* FCR - Flash Command Register */
79 #define FCR_CMD0 U(0xFF000000)
80 #define FCR_CMD0_SHIFT 24
81 #define FCR_CMD1 U(0x00FF0000)
82 #define FCR_CMD1_SHIFT 16
83 #define FCR_CMD2 U(0x0000FF00)
84 #define FCR_CMD2_SHIFT 8
85 #define FCR_CMD3 U(0x000000FF)
86 #define FCR_CMD3_SHIFT 0
87
88 /* FIR - Flash Instruction Register Opcode */
89 #define FIR_OP0 U(0xFC000000)
90 #define FIR_OP0_SHIFT 26
91 #define FIR_OP1 U(0x03F00000)
92 #define FIR_OP1_SHIFT 20
93 #define FIR_OP2 U(0x000FC000)
94 #define FIR_OP2_SHIFT 14
95 #define FIR_OP3 U(0x00003F00)
96 #define FIR_OP3_SHIFT 8
97 #define FIR_OP4 U(0x000000FC)
98 #define FIR_OP4_SHIFT 2
99 #define FIR_OP5 U(0xFC000000)
100 #define FIR_OP5_SHIFT 26
101 #define FIR_OP6 U(0x03F00000)
102 #define FIR_OP6_SHIFT 20
103
104 /* Instruction Opcode - 6 bits */
105 #define FIR_OP_NOP 0x00
106 #define FIR_OP_CA0 0x01 /* Issue current column address */
107 #define FIR_OP_CA1 0x02 /* Issue current column address */
108 #define FIR_OP_RA0 0x05 /* Issue current column address */
109 #define FIR_OP_RA1 0x06 /* Issue current column address */
110 #define FIR_OP_CMD0 0x09 /* Issue command from FCR[CMD0] */
111 #define FIR_OP_CMD1 0x0a /* Issue command from FCR[CMD1] */
112 #define FIR_OP_CMD2 0x0b /* Issue command from FCR[CMD2] */
113 #define FIR_OP_CMD3 0x0c /* Issue command from FCR[CMD3] */
114 #define FIR_OP_CW0 0x11 /* Wait then issue FCR[CMD0] */
115 #define FIR_OP_CW1 0x12 /* Wait then issue FCR[CMD1] */
116 #define FIR_OP_CW2 0x13 /* Wait then issue FCR[CMD1] */
117 #define FIR_OP_CW3 0x14 /* Wait then issue FCR[CMD1] */
118 #define FIR_OP_WBCD 0x19 /* Wait then read FBCR bytes */
119 #define FIR_OP_RBCD 0x1a /* Wait then read 1 or 2 bytes */
120 #define FIR_OP_BTRD 0x1b /* Wait then read 1 or 2 bytes */
121 #define FIR_OP_RDSTAT 0x1c /* Wait then read 1 or 2 bytes */
122 #define FIR_OP_NWAIT 0x1d /* Wait then read 1 or 2 bytes */
123 #define FIR_OP_WFR 0x1e /* Wait then read 1 or 2 bytes */
124
125 #define NAND_SEQ_STRT_FIR_STRT U(0x80000000)
126 #define NAND_SEQ_STRT_FIR_STRT_SHIFT 31
127
128 #define NAND_EVTER_STAT_FTOER U(0x08000000)
129 #define NAND_EVTER_STAT_WPER U(0x04000000)
130 #define NAND_EVTER_STAT_ECCER U(0x02000000)
131 #define NAND_EVTER_STAT_DQSER U(0x01000000)
132 #define NAND_EVTER_STAT_RCW_DN U(0x00008000)
133 #define NAND_EVTER_STAT_BOOT_DN U(0x00004000)
134 #define NAND_EVTER_STAT_RCW_DN U(0x00008000)
135 #define NAND_EVTER_STAT_OPC_DN U(0x80000000)
136 #define NAND_EVTER_STAT_BBI_SRCH_SEL U(0x00000800)
137 #define NCFGR_BOOT U(0x80000000)
138 #define NAND_AUTOBOOT_TRGR_RCW_LD U(0x80000000)
139 #define NAND_AUTOBOOT_TRGR_BOOT_LD U(0x20000000)
140
141 /* ECC ERROR STATUS Registers */
142 #define NAND_RCW_LD U(0x80000000)
143 #define NAND_BOOT_LD U(0x20000000)
144
145 /*Other Temp Defines */
146 /*256 bad Blocks supported */
147 #define BBT_SIZE 256
148
149 /*Standard NAND flash commands */
150 #define NAND_CMD_READ0 0
151 #define NAND_CMD_READ1 1
152 #define NAND_CMD_READOOB 0x50
153
154 /*Extended commands for large page devices */
155 #define NAND_CMD_READSTART 0x30
156
157 #define NAND_TIMEOUT_MS 40
158
159 #define EMPTY_VAL_CHECK U(0xFFFFFFFF)
160 #define EMPTY_VAL 0xFF
161
162
163 #define MAIN 0
164 #define SPARE 1
165
166 #define GOOD_BLK 1
167 #define BAD_BLK 0
168 #define DIV_2 2
169
170 #define ATTRIBUTE_PGSZ 0xa
171 #define ATTRIBUTE_PPB 0xb
172
173 #define CSPR_PORT_SIZE_8 (0x1 << 7)
174 #define CSPR_PORT_SIZE_16 (0x2 << 7)
175 #define CSPR_PORT_SIZE_32 (0x3 << 7)
176
177 /* NAND specific */
178 #define RCW_SRC_NAND_PORT_MASK U(0x00000080)
179
180 #define NAND_DEFAULT_CSPR U(0x00000053)
181 #define NAND_DEFAULT_CSOR U(0x0180C00C)
182 #define NAND_DEFAULT_EXT_CSPR U(0x00000000)
183 #define NAND_DEFAULT_EXT_CSOR U(0x00000000)
184 #define NAND_DEFAULT_FTIM0 U(0x181c0c10)
185 #define NAND_DEFAULT_FTIM1 U(0x5454141e)
186 #define NAND_DEFAULT_FTIM2 U(0x03808034)
187 #define NAND_DEFAULT_FTIM3 U(0x2c000000)
188
189 #define NAND_CSOR_ECC_MODE_DISABLE U(0x00000000)
190 #define NAND_CSOR_ECC_MODE0 U(0x84000000)
191 #define NAND_CSOR_ECC_MODE1 U(0x94000000)
192 #define NAND_CSOR_ECC_MODE2 U(0xa4000000)
193 #define NAND_CSOR_ECC_MODE3 U(0xb4000000)
194 #define NAND_CSOR_PAGE_SIZE_2K (0x1 << 19)
195 #define NAND_CSOR_PAGE_SIZE_4K (0x2 << 19)
196 #define NAND_CSOR_PAGE_SIZE_8K (0x3 << 19)
197 #define NAND_CSOR_PAGE_SIZE_16K (0x4 << 19)
198 #define NAND_CSOR_PPB_64 (0x1 << 8)
199 #define NAND_CSOR_PPB_128 (0x2 << 8)
200 #define NAND_CSOR_PPB_256 (0x3 << 8)
201 #define NAND_CSOR_PPB_512 (0x4 << 8)
202
203 /* BBI INDICATOR for NAND_2K(CFG_RCW_SRC[1]) for
204 * devices greater than 2K page size(CFG_RCW_SRC[3])
205 */
206 #define RCW_SRC_NAND_BBI_MASK U(0x00000008)
207 #define RCW_SRC_NAND_BBI_MASK_NAND_2K U(0x00000002)
208 #define NAND_BBI_ONFI_2K (0x1 << 1)
209 #define NAND_BBI_ONFI (0x1 << 3)
210
211 #define RCW_SRC_NAND_PAGE_MASK U(0x00000070)
212 #define RCW_SRC_NAND_PAGE_MASK_NAND_2K U(0x0000000C)
213 #define NAND_2K_XXX 0x00
214 #define NAND_2K_64 0x04
215 #define NAND_2K_128 0x08
216 #define NAND_4K_128 0x10
217 #define NAND_4K_256 0x20
218 #define NAND_4K_512 0x30
219 #define NAND_8K_128 0x40
220 #define NAND_8K_256 0x50
221 #define NAND_8K_512 0x60
222 #define NAND_16K_512 0x70
223 #define BLOCK_LEN_2K 2048
224
225 #define RCW_SRC_NAND_ECC_MASK U(0x00000007)
226 #define RCW_SRC_NAND_ECC_MASK_NAND_2K U(0x00000001)
227 #define NAND_ECC_DISABLE 0x0
228 #define NAND_ECC_4_520 0x1
229 #define NAND_ECC_8_528 0x5
230 #define NAND_ECC_24_1K 0x6
231 #define NAND_ECC_40_1K 0x7
232
233 #define NAND_SPARE_2K U(0x00000040)
234 #define NAND_SPARE_4K_ECC_M0 U(0x00000080)
235 #define NAND_SPARE_4K_ECC_M1 U(0x000000D2)
236 #define NAND_SPARE_4K_ECC_M2 U(0x000000B0)
237 #define NAND_SPARE_4K_ECC_M3 U(0x00000120)
238 #define NAND_SPARE_8K_ECC_M0 U(0x00000088)
239 #define NAND_SPARE_8K_ECC_M1 U(0x00000108)
240 #define NAND_SPARE_8K_ECC_M2 U(0x00000158)
241 #define NAND_SPARE_8K_ECC_M3 U(0x00000238)
242 #define NAND_SPARE_16K_ECC_M0 U(0x00000108)
243 #define NAND_SPARE_16K_ECC_M1 U(0x00000208)
244 #define NAND_SPARE_16K_ECC_M2 U(0x000002A8)
245 #define NAND_SPARE_16K_ECC_M3 U(0x00000468)
246
247 struct nand_info {
248 uintptr_t ifc_register_addr;
249 uintptr_t ifc_region_addr;
250 uint32_t page_size;
251 uint32_t port_size;
252 uint32_t blk_size;
253 uint32_t ppb;
254 uint32_t pi_width; /* Bits Required to index a page in block */
255 uint32_t ral;
256 uint32_t ibr_flow;
257 uint32_t bbt[BBT_SIZE];
258 uint32_t lgb; /* Last Good Block */
259 uint32_t bbt_max; /* Total entries in bbt */
260 uint32_t bzero_good;
261 uint8_t bbs;
262 uint8_t bad_marker_loc;
263 uint8_t onfi_dev_flag;
264 uint8_t init_time_boot_flag;
265 uint8_t *buf;
266 };
267
268 struct ifc_regs {
269 uint32_t ext_cspr;
270 uint32_t cspr;
271 uint32_t csor;
272 uint32_t ext_csor;
273 };
274
275 struct sec_nand_info {
276 uint32_t cspr_port_size;
277 uint32_t csor_ecc_mode;
278 uint32_t csor_page_size;
279 uint32_t csor_ppb;
280 uint32_t ext_csor_spare_size;
281 uint32_t onfi_flag;
282 };
283
284 struct sec_nor_info {
285 uint32_t cspr_port_size;
286 uint32_t csor_nor_mode;
287 uint32_t csor_adm_shift;
288 uint32_t port_size;
289 uint32_t addr_bits;
290 };
291
292 enum ifc_chip_sel {
293 IFC_CS0,
294 IFC_CS1,
295 IFC_CS2,
296 IFC_CS3,
297 IFC_CS4,
298 IFC_CS5,
299 IFC_CS6,
300 IFC_CS7,
301 };
302
303 enum ifc_ftims {
304 IFC_FTIM0,
305 IFC_FTIM1,
306 IFC_FTIM2,
307 IFC_FTIM3,
308 };
309
310 #ifdef NXP_IFC_BE
311 #define nand_in32(a) bswap32(mmio_read_32((uintptr_t)a))
312 #define nand_out32(a, v) mmio_write_32((uintptr_t)a, bswap32(v))
313 #else
314 #define nand_in32(a) mmio_read_32((uintptr_t)a)
315 #define nand_out32(a, v) mmio_write_32((uintptr_t)a, v)
316 #endif
317
318 /* Read Write on IFC registers */
write_reg(struct nand_info * nand,uint32_t reg,uint32_t val)319 static inline void write_reg(struct nand_info *nand, uint32_t reg, uint32_t val)
320 {
321 nand_out32(nand->ifc_register_addr + reg, val);
322 }
323
read_reg(struct nand_info * nand,uint32_t reg)324 static inline uint32_t read_reg(struct nand_info *nand, uint32_t reg)
325 {
326 return nand_in32(nand->ifc_register_addr + reg);
327 }
328
329 #endif /* IFC_H */
330