1 /*
2 * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <stdint.h>
8
9 #include <common/debug.h>
10
11 #include <rcar_def.h>
12
13 #include "../qos_common.h"
14 #include "../qos_reg.h"
15 #include "qos_init_h3_v11.h"
16
17 #define RCAR_QOS_VERSION "rev.0.37"
18
19 #include "qos_init_h3_v11_mstat.h"
20
21 struct rcar_gen3_dbsc_qos_settings h3_v11_qos[] = {
22 /* BUFCAM settings */
23 /* DBSC_DBCAM0CNF0 not set */
24 { DBSC_DBCAM0CNF1, 0x00044218 },
25 { DBSC_DBCAM0CNF2, 0x000000F4 },
26 /* DBSC_DBCAM0CNF3 not set */
27 { DBSC_DBSCHCNT0, 0x080F0037 },
28 { DBSC_DBSCHCNT1, 0x00001010 },
29 { DBSC_DBSCHSZ0, 0x00000001 },
30 { DBSC_DBSCHRW0, 0x22421111 },
31
32 /* DDR3 */
33 { DBSC_SCFCTST2, 0x012F1123 },
34
35 /* QoS Settings */
36 { DBSC_DBSCHQOS00, 0x0000F000 },
37 { DBSC_DBSCHQOS01, 0x0000E000 },
38 { DBSC_DBSCHQOS02, 0x00007000 },
39 { DBSC_DBSCHQOS03, 0x00000000 },
40 { DBSC_DBSCHQOS40, 0x00000E00 },
41 { DBSC_DBSCHQOS41, 0x00000DFF },
42 { DBSC_DBSCHQOS42, 0x00000400 },
43 { DBSC_DBSCHQOS43, 0x00000200 },
44 { DBSC_DBSCHQOS90, 0x00000C00 },
45 { DBSC_DBSCHQOS91, 0x00000BFF },
46 { DBSC_DBSCHQOS92, 0x00000400 },
47 { DBSC_DBSCHQOS93, 0x00000200 },
48 { DBSC_DBSCHQOS130, 0x00000980 },
49 { DBSC_DBSCHQOS131, 0x0000097F },
50 { DBSC_DBSCHQOS132, 0x00000300 },
51 { DBSC_DBSCHQOS133, 0x00000180 },
52 { DBSC_DBSCHQOS140, 0x00000800 },
53 { DBSC_DBSCHQOS141, 0x000007FF },
54 { DBSC_DBSCHQOS142, 0x00000300 },
55 { DBSC_DBSCHQOS143, 0x00000180 },
56 { DBSC_DBSCHQOS150, 0x000007D0 },
57 { DBSC_DBSCHQOS151, 0x000007CF },
58 { DBSC_DBSCHQOS152, 0x000005D0 },
59 { DBSC_DBSCHQOS153, 0x000003D0 },
60 };
61
qos_init_h3_v11(void)62 void qos_init_h3_v11(void)
63 {
64 rcar_qos_dbsc_setting(h3_v11_qos, ARRAY_SIZE(h3_v11_qos), false);
65
66 /* DRAM Split Address mapping */
67 #if (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH) || \
68 (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_AUTO)
69 NOTICE("BL2: DRAM Split is 4ch\n");
70 io_write_32(AXI_ADSPLCR0, ADSPLCR0_ADRMODE_DEFAULT
71 | ADSPLCR0_SPLITSEL(0xFFU)
72 | ADSPLCR0_AREA(0x1BU)
73 | ADSPLCR0_SWP);
74 io_write_32(AXI_ADSPLCR1, 0x00000000U);
75 io_write_32(AXI_ADSPLCR2, 0xA8A90000U);
76 io_write_32(AXI_ADSPLCR3, 0x00000000U);
77 #elif RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH
78 NOTICE("BL2: DRAM Split is 2ch\n");
79 io_write_32(AXI_ADSPLCR0, 0x00000000U);
80 io_write_32(AXI_ADSPLCR1, ADSPLCR0_ADRMODE_DEFAULT
81 | ADSPLCR0_SPLITSEL(0xFFU)
82 | ADSPLCR0_AREA(0x1BU)
83 | ADSPLCR0_SWP);
84 io_write_32(AXI_ADSPLCR2, 0x00000000U);
85 io_write_32(AXI_ADSPLCR3, 0x00000000U);
86 #else
87 NOTICE("BL2: DRAM Split is OFF\n");
88 #endif
89
90 #if !(RCAR_QOS_TYPE == RCAR_QOS_NONE)
91 #if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
92 NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION);
93 #endif
94
95 /* AR Cache setting */
96 io_write_32(0xE67D1000U, 0x00000100U);
97 io_write_32(0xE67D1008U, 0x00000100U);
98
99 /* Resource Alloc setting */
100 #if RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH
101 io_write_32(QOSCTRL_RAS, 0x00000020U);
102 #else
103 io_write_32(QOSCTRL_RAS, 0x00000040U);
104 #endif
105 io_write_32(QOSCTRL_FIXTH, 0x000F0005U);
106 io_write_32(QOSCTRL_REGGD, 0x00000000U);
107 #if RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH
108 io_write_64(QOSCTRL_DANN, 0x0101010102020201UL);
109 io_write_32(QOSCTRL_DANT, 0x00181008U);
110 #else
111 io_write_64(QOSCTRL_DANN, 0x0101000004040401UL);
112 io_write_32(QOSCTRL_DANT, 0x003C2010U);
113 #endif
114 io_write_32(QOSCTRL_EC, 0x00080001U); /* need for H3 v1.* */
115 io_write_64(QOSCTRL_EMS, 0x0000000000000000UL);
116 io_write_32(QOSCTRL_INSFC, 0xC7840001U);
117 io_write_32(QOSCTRL_BERR, 0x00000000U);
118 io_write_32(QOSCTRL_RACNT0, 0x00000000U);
119
120 /* QOSBW setting */
121 io_write_32(QOSCTRL_SL_INIT,
122 SL_INIT_REFFSSLOT | SL_INIT_SLOTSSLOT | SL_INIT_SSLOTCLK);
123 io_write_32(QOSCTRL_REF_ARS, 0x00330000U);
124
125 /* QOSBW SRAM setting */
126 uint32_t i;
127
128 for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
129 io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]);
130 io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]);
131 }
132 for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
133 io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]);
134 io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]);
135 }
136
137 /* 3DG bus Leaf setting */
138 io_write_32(0xFD820808U, 0x00001234U);
139 io_write_32(0xFD820800U, 0x0000003FU);
140 io_write_32(0xFD821800U, 0x0000003FU);
141 io_write_32(0xFD822800U, 0x0000003FU);
142 io_write_32(0xFD823800U, 0x0000003FU);
143 io_write_32(0xFD824800U, 0x0000003FU);
144 io_write_32(0xFD825800U, 0x0000003FU);
145 io_write_32(0xFD826800U, 0x0000003FU);
146 io_write_32(0xFD827800U, 0x0000003FU);
147
148 /* VIO bus Leaf setting */
149 io_write_32(0xFEB89800, 0x00000001U);
150 io_write_32(0xFEB8A800, 0x00000001U);
151 io_write_32(0xFEB8B800, 0x00000001U);
152 io_write_32(0xFEB8C800, 0x00000001U);
153
154 /* HSC bus Leaf setting */
155 io_write_32(0xE6430800, 0x00000001U);
156 io_write_32(0xE6431800, 0x00000001U);
157 io_write_32(0xE6432800, 0x00000001U);
158 io_write_32(0xE6433800, 0x00000001U);
159
160 /* MP bus Leaf setting */
161 io_write_32(0xEC620800, 0x00000001U);
162 io_write_32(0xEC621800, 0x00000001U);
163
164 /* PERIE bus Leaf setting */
165 io_write_32(0xE7760800, 0x00000001U);
166 io_write_32(0xE7768800, 0x00000001U);
167
168 /* PERIW bus Leaf setting */
169 io_write_32(0xE6760800, 0x00000001U);
170 io_write_32(0xE6768800, 0x00000001U);
171
172 /* RT bus Leaf setting */
173 io_write_32(0xFFC50800, 0x00000001U);
174 io_write_32(0xFFC51800, 0x00000001U);
175
176 /* CCI bus Leaf setting */
177 uint32_t modemr = io_read_32(RCAR_MODEMR);
178
179 modemr &= MODEMR_BOOT_CPU_MASK;
180
181 if ((modemr == MODEMR_BOOT_CPU_CA57) ||
182 (modemr == MODEMR_BOOT_CPU_CA53)) {
183 io_write_32(0xF1300800, 0x00000001U);
184 io_write_32(0xF1340800, 0x00000001U);
185 io_write_32(0xF1380800, 0x00000001U);
186 io_write_32(0xF13C0800, 0x00000001U);
187 }
188
189 /* Resource Alloc start */
190 io_write_32(QOSCTRL_RAEN, 0x00000001U);
191
192 /* QOSBW start */
193 io_write_32(QOSCTRL_STATQC, 0x00000001U);
194 #else
195 NOTICE("BL2: QoS is None\n");
196
197 /* Resource Alloc setting */
198 io_write_32(QOSCTRL_EC, 0x00080001U); /* need for H3 v1.* */
199 #endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */
200 }
201