1 /*
2 * Copyright (c) 2021, Renesas Electronics Corporation. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <stdint.h>
8
9 #include <common/debug.h>
10 #include <lib/mmio.h>
11
12 #include "qos_init_g2n_v10.h"
13
14 #include "../qos_common.h"
15 #include "../qos_reg.h"
16
17 #define RCAR_QOS_VERSION "rev.0.09"
18
19 #define REF_ARS_ARBSTOPCYCLE_G2N (((SL_INIT_SSLOTCLK_G2N) - 5U) << 16U)
20
21 #define QOSWT_TIME_BANK0 20000000U /* unit:ns */
22
23 #define QOSWT_WTEN_ENABLE 0x1U
24
25 #define OSWT_WTREF_SLOT0_EN_REQ1_SLOT 3U
26 #define OSWT_WTREF_SLOT0_EN_REQ2_SLOT 9U
27 #define QOSWT_WTREF_SLOT0_EN ((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | \
28 (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
29 #define QOSWT_WTREF_SLOT1_EN QOSWT_WTREF_SLOT0_EN
30
31 #define QOSWT_WTSET0_REQ_SSLOT0 5U
32 #define WT_BASE_SUB_SLOT_NUM0 12U
33 #define QOSWT_WTSET0_PERIOD0_G2N ((QOSWT_TIME_BANK0 / QOSWT_WTSET0_CYCLE_G2N) - 1U)
34 #define QOSWT_WTSET0_SSLOT0 (QOSWT_WTSET0_REQ_SSLOT0 - 1U)
35 #define QOSWT_WTSET0_SLOTSLOT0 (WT_BASE_SUB_SLOT_NUM0 - 1U)
36
37 #define QOSWT_WTSET1_PERIOD1_G2N QOSWT_WTSET0_PERIOD0_G2N
38 #define QOSWT_WTSET1_SSLOT1 QOSWT_WTSET0_SSLOT0
39 #define QOSWT_WTSET1_SLOTSLOT1 QOSWT_WTSET0_SLOTSLOT0
40
41 #if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
42
43 #if RCAR_REF_INT == RCAR_REF_DEFAULT
44 #include "qos_init_g2n_v10_mstat195.h"
45 #else
46 #include "qos_init_g2n_v10_mstat390.h"
47 #endif
48
49 #if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
50
51 #if RCAR_REF_INT == RCAR_REF_DEFAULT
52 #include "qos_init_g2n_v10_qoswt195.h"
53 #else
54 #include "qos_init_g2n_v10_qoswt390.h"
55 #endif
56
57 #endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
58 #endif
59
60 static const struct rcar_gen3_dbsc_qos_settings g2n_v10_qos[] = {
61 /* BUFCAM settings */
62 { DBSC_DBCAM0CNF1, 0x00043218U },
63 { DBSC_DBCAM0CNF2, 0x000000F4U },
64 { DBSC_DBSCHCNT0, 0x000F0037U },
65 { DBSC_DBSCHSZ0, 0x00000001U },
66 { DBSC_DBSCHRW0, 0x22421111U },
67
68 /* DDR3 */
69 { DBSC_SCFCTST2, 0x012F1123U },
70
71 /* QoS Settings */
72 { DBSC_DBSCHQOS00, 0x00000F00U },
73 { DBSC_DBSCHQOS01, 0x00000B00U },
74 { DBSC_DBSCHQOS02, 0x00000000U },
75 { DBSC_DBSCHQOS03, 0x00000000U },
76 { DBSC_DBSCHQOS40, 0x00000300U },
77 { DBSC_DBSCHQOS41, 0x000002F0U },
78 { DBSC_DBSCHQOS42, 0x00000200U },
79 { DBSC_DBSCHQOS43, 0x00000100U },
80 { DBSC_DBSCHQOS90, 0x00000100U },
81 { DBSC_DBSCHQOS91, 0x000000F0U },
82 { DBSC_DBSCHQOS92, 0x000000A0U },
83 { DBSC_DBSCHQOS93, 0x00000040U },
84 { DBSC_DBSCHQOS130, 0x00000100U },
85 { DBSC_DBSCHQOS131, 0x000000F0U },
86 { DBSC_DBSCHQOS132, 0x000000A0U },
87 { DBSC_DBSCHQOS133, 0x00000040U },
88 { DBSC_DBSCHQOS140, 0x000000C0U },
89 { DBSC_DBSCHQOS141, 0x000000B0U },
90 { DBSC_DBSCHQOS142, 0x00000080U },
91 { DBSC_DBSCHQOS143, 0x00000040U },
92 { DBSC_DBSCHQOS150, 0x00000040U },
93 { DBSC_DBSCHQOS151, 0x00000030U },
94 { DBSC_DBSCHQOS152, 0x00000020U },
95 { DBSC_DBSCHQOS153, 0x00000010U },
96 };
97
qos_init_g2n_v10(void)98 void qos_init_g2n_v10(void)
99 {
100 rzg_qos_dbsc_setting(g2n_v10_qos, ARRAY_SIZE(g2n_v10_qos), true);
101
102 /* DRAM Split Address mapping */
103 #if RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH
104 #if RCAR_LSI == RZ_G2N
105 #error "Don't set DRAM Split 4ch(G2N)"
106 #else
107 ERROR("DRAM Split 4ch not supported.(G2N)");
108 panic();
109 #endif
110 #elif (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH)
111 #if RCAR_LSI == RZ_G2N
112 #error "Don't set DRAM Split 2ch(G2N)"
113 #else
114 ERROR("DRAM Split 2ch not supported.(G2N)");
115 panic();
116 #endif
117 #else
118 NOTICE("BL2: DRAM Split is OFF\n");
119 #endif
120
121 #if !(RCAR_QOS_TYPE == RCAR_QOS_NONE)
122 #if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
123 NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION);
124 #endif
125
126 #if RCAR_REF_INT == RCAR_REF_DEFAULT
127 NOTICE("BL2: DRAM refresh interval 1.95 usec\n");
128 #else
129 NOTICE("BL2: DRAM refresh interval 3.9 usec\n");
130 #endif
131
132 #if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
133 NOTICE("BL2: Periodic Write DQ Training\n");
134 #endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
135
136 mmio_write_32(QOSCTRL_RAS, 0x00000028U);
137 mmio_write_64(QOSCTRL_DANN, 0x0402000002020201UL);
138 mmio_write_32(QOSCTRL_DANT, 0x00100804U);
139 mmio_write_32(QOSCTRL_FSS, 0x0000000AU);
140 mmio_write_32(QOSCTRL_INSFC, 0x06330001U);
141 mmio_write_32(QOSCTRL_EARLYR, 0x00000001U);
142 mmio_write_32(QOSCTRL_RACNT0, 0x00010003U);
143
144 mmio_write_32(QOSCTRL_SL_INIT, SL_INIT_REFFSSLOT |
145 SL_INIT_SLOTSSLOT | SL_INIT_SSLOTCLK_G2N);
146 mmio_write_32(QOSCTRL_REF_ARS, REF_ARS_ARBSTOPCYCLE_G2N);
147
148 uint32_t i;
149
150 for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
151 mmio_write_64(QOSBW_FIX_QOS_BANK0 + i * 8U, mstat_fix[i]);
152 mmio_write_64(QOSBW_FIX_QOS_BANK1 + i * 8U, mstat_fix[i]);
153 }
154 for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
155 mmio_write_64(QOSBW_BE_QOS_BANK0 + i * 8U, mstat_be[i]);
156 mmio_write_64(QOSBW_BE_QOS_BANK1 + i * 8U, mstat_be[i]);
157 }
158 #if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
159 for (i = 0U; i < ARRAY_SIZE(qoswt_fix); i++) {
160 mmio_write_64(QOSWT_FIX_WTQOS_BANK0 + i * 8U, qoswt_fix[i]);
161 mmio_write_64(QOSWT_FIX_WTQOS_BANK1 + i * 8U, qoswt_fix[i]);
162 }
163 for (i = 0U; i < ARRAY_SIZE(qoswt_be); i++) {
164 mmio_write_64(QOSWT_BE_WTQOS_BANK0 + i * 8U, qoswt_be[i]);
165 mmio_write_64(QOSWT_BE_WTQOS_BANK1 + i * 8U, qoswt_be[i]);
166 }
167 #endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
168
169 /* RT bus Leaf setting */
170 mmio_write_32(RT_ACT0, 0x00000000U);
171 mmio_write_32(RT_ACT1, 0x00000000U);
172
173 /* CCI bus Leaf setting */
174 mmio_write_32(CPU_ACT0, 0x00000003U);
175 mmio_write_32(CPU_ACT1, 0x00000003U);
176
177 mmio_write_32(QOSCTRL_RAEN, 0x00000001U);
178
179 #if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
180 /* re-write training setting */
181 mmio_write_32(QOSWT_WTREF, ((QOSWT_WTREF_SLOT1_EN << 16) | QOSWT_WTREF_SLOT0_EN));
182 mmio_write_32(QOSWT_WTSET0, ((QOSWT_WTSET0_PERIOD0_G2N << 16) |
183 (QOSWT_WTSET0_SSLOT0 << 8) | QOSWT_WTSET0_SLOTSLOT0));
184 mmio_write_32(QOSWT_WTSET1, ((QOSWT_WTSET1_PERIOD1_G2N << 16) |
185 (QOSWT_WTSET1_SSLOT1 << 8) | QOSWT_WTSET1_SLOTSLOT1));
186
187 mmio_write_32(QOSWT_WTEN, QOSWT_WTEN_ENABLE);
188 #endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
189
190 mmio_write_32(QOSCTRL_STATQC, 0x00000001U);
191 #else
192 NOTICE("BL2: QoS is None\n");
193
194 mmio_write_32(QOSCTRL_RAEN, 0x00000001U);
195 #endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */
196 }
197